Die Stack Carrier Structure With Composite Vias for Precise Pad Alignment

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Solution Overview

Problem

As semiconductor devices become smaller, accurately positioning the electrical connecting pad becomes increasingly difficult, which can adversely affect the conductive performance of the devices.

Innovation Solution

A semiconductor device design that includes a die stack, an intervening bonding layer, and a carrier structure with a heat dissipation unit featuring composite vias and conductive plates, where the composite vias are surrounded by protection layers and connected through conductive portions to ensure precise positioning and improved conductivity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If semiconductor devices are miniaturized to reduce size and increase integration, then device functionality and integration density are improved, but positioning precision of electrical connecting pads deteriorates

Engineering Contradiction:
Improvedevice sizeVSAvoidpositioning precision of electrical connecting pad
Core Design Contradiction:
Volume of moving objectVSManufacturing precision

Solution Approach 1:

The invention divides the electrical connection function into multiple components: through-semiconductor vias extend through the semiconductor layer to provide vertical conduction paths, while separate electrical connecting pads are positioned on the semiconductor layer. This segmentation allows each component to be optimized independently, with vias providing robust electrical pathways and pads being precisely positioned at specific locations to maintain accurate alignment even as device dimensions are reduced.

Inventive Principle:
Principle #1Segmentation

2Reliability

If through-semiconductor vias are used to reduce electrical resistance and improve conduction efficiency, then electrical conductivity is improved, but device complexity increases

Engineering Contradiction:
Improveconductive performanceVSAvoidstructural complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The through-semiconductor vias serve multiple functions simultaneously: they provide low-resistance vertical electrical conduction paths between different layers, act as mechanical support structures, and enable precise positioning of electrical connecting pads. By combining these functions into a single structural element, the invention improves conductive performance while minimizing the increase in overall device complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The design allows for precise placement of conductive connecting portions, enhancing the conductive performance of semiconductor devices by reducing the challenges associated with miniaturization.

Implementation Method 1

The carrier structure includes a heat dissipation unit configured to transfer heat generated from the die stack. The heat dissipation unit includes composite vias and conductive plates.

Methodology Applied
Scientific EffectHeat transfer: Conduction (thermal)

Data Source

PatentUS12176267B2Semiconductor device and method for manufacturing the same
Publication Date: 2024.12.24 NAN YA TECH
  • US12176267B2 patent drawing
  • US12176267B2 patent drawing
  • US12176267B2 patent drawing

AI summary

The present disclosure provides a semiconductor device. The semiconductor device includes a die stack, an intervening bonding layer, and a carrier structure. The intervening bonding layer is positioned on the die stack. The carrier structure is disposed on the intervening bonding layer opposite to the die stack. The carrier structure includes a heat dissipation unit configured to transfer heat generated from the die stack. The heat dissipation unit includes composite vias and conductive plates. Each of the composite vias includes a first through semiconductor via and a second through semiconductor via. The conductive plates are couple to the composite vias.