Semiconductor Die Stacks With Dielectric Cushioning
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Solution Overview
Problem
Current semiconductor die assembly technologies face challenges in achieving high circuit density, thermal performance, mechanical strength, and cost-effectiveness, particularly in stacked die configurations like the Micropillar Grid Array Package (MPGA), where fragile semiconductor dice require robust mechanical protection and efficient heat dissipation.
Innovation Solution
A semiconductor die assembly method involving a base wafer with thermally conductive elements, where semiconductor dice with conductive through vias are stacked and encapsulated with a dielectric material, providing mechanical protection and enhanced thermal performance, and the base wafer is thinned to reduce package height, enabling higher throughput and reduced costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If semiconductor dice are stacked vertically to increase circuit density, then circuit density is improved, but mechanical strength deteriorates due to fragile dice requiring robust protection
Solution Approach 1:
The patent applies beforehand cushioning by introducing a dielectric material between the semiconductor dice before final encapsulation. This dielectric material acts as a cushioning layer that provides mechanical protection to the fragile dice while maintaining the vertical stacking configuration for high circuit density.
Solution Approach 2:
The dielectric material serves as an intermediary between the semiconductor dice, providing both mechanical support and electrical isolation. This intermediary element enables the fragile dice to be stacked vertically without direct contact, thereby maintaining both high circuit density and mechanical strength.
2Strength
If conventional encapsulation methods are used, then mechanical protection is provided, but thermal performance deteriorates due to insufficient heat dissipation
Solution Approach 1:
The patent applies parameter changes by selecting a dielectric material with specific thermal conductivity properties that differ from conventional encapsulants. The dielectric material is chosen to have improved thermal performance parameters, enabling efficient heat dissipation while maintaining mechanical protection of the stacked dice.
Solution Approach 2:
The patent uses composite materials by combining the dielectric material with the encapsulant material. This composite structure provides both mechanical protection from the encapsulant and improved thermal performance from the dielectric material, resolving the contradiction between protection and heat dissipation.
3Strength
If base wafer is not thinned, then structural support is maintained, but package height increases reducing manufacturing efficiency
Solution Approach 1:
The patent applies parameter changes by controlling the thickness parameter of the base wafer. The base wafer is thinned to an optimized thickness that maintains sufficient structural support for the stacked dice while reducing the overall package height. This enables more efficient manufacturing and handling of the semiconductor device.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enhances thermal performance, mechanical strength, and manufacturing efficiency, allowing for higher circuit density and reduced packaging costs while protecting fragile dice and enabling wafer-level testing and handling.
Implementation Method 1
providing a dielectric material between the semiconductor dice
Implementation Method 2
base wafer with thermally conductive elements protruding therefrom
Data Source
Figure 1A~1F
Figure 1G~1J
Figure 1K~2D
AI summary
Methods of fabricating multi-die assemblies including a wafer segment having no integrated circuitry thereon and having a plurality of vertically stacked dice thereon electrically interconnected by conductive through vias, resulting multi-die assemblies, and semiconductor devices comprising such multi-die assemblies. The wafer segment may function as a heat sink to enhance heat transfer from the stacked dice in the resulting multi-die assembly. The die stacks are fabricated at the wafer level on a base wafer, from which the wafer segment and die stacks are singulated after at least peripheral encapsulation.