Die Stack Package Structure With Hybrid Bonding and Encapsulation
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Solution Overview
Problem
The semiconductor industry faces challenges in packaging System-on-Integrated-Circuit (SoIC) components due to limitations in current packaging techniques, which affect miniaturization, speed, bandwidth, power consumption, and latency.
Innovation Solution
A method for fabricating a die stack structure involving hybrid bonding of top and bottom tier semiconductor dies with a redistribution circuit structure, followed by encapsulation and sawing processes to create a compact, reliable integrated circuit (IC) or system-on-integrated-chip (SoIC) die, suitable for flip-chip applications and further packaging.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional packaging techniques are used for SoIC components, then the packaging process can be completed with existing methods, but miniaturization, speed, bandwidth, power consumption, and latency are limited
Solution Approach 1:
The semiconductor manufacturing process is segmented into separate wafer fabrication and packaging phases, allowing independent optimization of each. Multiple semiconductor wafers are fabricated separately and then integrated during packaging to form the final SoIC product, enabling higher integration density while maintaining reliability through controlled assembly processes
Solution Approach 2:
The patent transitions from planar 2D packaging to three-dimensional stacked packaging architecture. Multiple semiconductor dies are stacked vertically in layers with interconnect structures enabling electrical connections between tiers, dramatically increasing integration density by utilizing the vertical dimension rather than only horizontal expansion
2Productivity
If multiple semiconductor dies are stacked to increase integration density, then miniaturization is achieved, but delamination risk increases
Solution Approach 1:
Multiple semiconductor dies and interconnect structures are merged into a single integrated three-dimensional stack during the packaging process. The dies are bonded together with precise alignment to form a unified structure where electrical connections and mechanical support are integrated, reducing the risk of delamination through unified construction rather than separate assembly steps
Solution Approach 2:
Wafer-level preparations are performed before stacking, including forming interconnect structures, conducting preliminary alignment, and preparing bonding surfaces. These preliminary actions ensure that when dies are stacked, they achieve optimal alignment and bonding strength from the outset, preventing delamination issues that would arise from post-assembly adjustments
Data Source
AI summary
A die stack structure including a first semiconductor die, a second semiconductor die, an insulating encapsulation and a redistribution circuit structure is provided. The first semiconductor die includes a first semiconductor substrate including a first portion and a second portion, a first interconnect structure and a first bonding structure. The first interconnect structure is disposed on a top surface of the second portion, a lateral dimension of the first portion is greater than a lateral dimension of the top surface of the second portion. The second semiconductor die is disposed on the first semiconductor die and includes a second bonding structure, the second semiconductor die is electrically connected with the first semiconductor die through the first and second bonding structures. The insulating encapsulation is disposed on the first portion and laterally encapsulating the second portion and the second semiconductor die. The redistribution circuit structure is electrically connected with the first and second semiconductor dies, and the lateral dimension of the first portion is greater than a lateral dimension of the redistribution circuit structure.