Conformal Die-Stack Interconnects Without Wire Bonds
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Solution Overview
Problem
Current interconnect structures in semiconductor packages, such as wire bonds, face challenges in miniaturization and noise tolerance, particularly in 3D packaging, leading to increased package size and variability that hinders high-speed applications.
Innovation Solution
The use of lithographic and deposition processes to form conformal interconnect structures that electrically couple components without wire bonds, utilizing sloped sidewalls to enable continuous conductive traces between stacked dies, reducing package size and noise variability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If wire bonds are used to interconnect dies in a die stack, then flexibility and ease of manufacture are improved, but package size increases and manufacturing precision deteriorates due to lack of standardization
Solution Approach 1:
The patent replaces the mechanical wire bonding system with a lithographically-defined conductive trace system. Instead of using physical wire bonds that require manual or semi-automatic bonding processes, the interconnect structure is formed through lithographic patterning and deposition processes, eliminating the mechanical assembly step and enabling precise, standardized dimensions to be defined by the lithography process rather than by wire manufacturing tolerances.
Solution Approach 2:
The patent changes the dimensional parameters of the interconnect structure from being wire-bond-determined to being lithography-determined. The conductive traces are formed with precise widths, spacing, and positions defined by photolithography masks and deposition thickness control, enabling standardized dimensions (e.g., 10 micrometer width, 50 micrometer spacing) that are much more precise than wire bond tolerances.
2Ease of manufacture
If wire bonds are used to interconnect dies in a die stack, then ease of manufacture is improved, but package size increases
Solution Approach 1:
The patent transitions the interconnect structure from a three-dimensional wire bond configuration (wires extending vertically between dies) to a two-dimensional planar conductive trace configuration (traces formed on and between die surfaces). This dimensional change allows the interconnect structure to be integrated within the package footprint rather than extending outward, reducing the overall package height and size.
3Adaptability or versatility
If wire bonds are used to interconnect dies in a die stack, then flexibility for different architectures is improved, but reliability deteriorates due to noise and variability
Solution Approach 1:
The patent creates a universal lithographically-defined interconnect structure that can be adapted to different die architectures and packaging configurations. The conductive trace system can be patterned in various geometries and configurations to suit different electrical connection requirements, replacing multiple wire bond configurations with a single versatile lithographic process that maintains reliability through standardized, controlled dimensions.
4Device complexity
If conventional interconnect structures are used, then manufacturing simplicity is improved, but productivity deteriorates due to increased package size and assembly complexity
Solution Approach 1:
The patent merges the interconnect structure formation with the die fabrication and packaging processes. The conductive traces are formed using lithographic and deposition processes that can be integrated into existing semiconductor manufacturing workflows, eliminating separate wire bonding assembly steps and enabling higher throughput through consolidated manufacturing processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces package size, enhances reliability, and allows for high-speed applications by eliminating the need for wire bonding and minimizing noise issues, while also simplifying and cost-effectively manufacturing semiconductor packages.
Implementation Method 1
fabricating an interconnect structure using lithographic and deposition processes
Implementation Method 2
fabricating an interconnect structure using lithographic and deposition processes
Implementation Method 3
fabricating an interconnect structure using lithographic and deposition processes
Data Source
AI summary
Embodiments described herein provide techniques of forming an interconnect structure using lithographic and deposition processes. The interconnect structure can be used to couple components of a semiconductor package. For one example, a semiconductor package includes a die stack and an interconnect structure formed on the die stack. The die stack comprises a plurality of dies. Each die in the die stack comprises: a first surface; a second surface opposite the first surface; sidewall surfaces coupling the first surface to the second surface; and a pad on the first surface. A one sidewall surface of one of the dies has a sloped profile. The semiconductor package also includes an interconnect structure positioned on the first surfaces and the sidewall with the sloped profile. In this semiconductor package, the interconnect structure electrically couples the pad on each of the dies to each other.