Semiconductor Die Stack Lattice Offset for Wafer Bond Stress Relief

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Solution Overview

Problem

Semiconductor packages with wafers bonded in the same lattice direction are prone to warpage and fracture due to insufficient stress resistance, leading to defects and fragmentation during high-temperature processes.

Innovation Solution

Orienting the crystal lattices of bonded semiconductor wafers in different directions, with an angle greater than 0.5 degrees, to reduce stress accumulation and enhance stress resistance in the wafer-to-wafer bond.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Strength

If semiconductor wafers are bonded in the same lattice direction, then the bonding process is simple and alignment is easy, but the stress resistance is insufficient leading to warpage and fracture

Engineering Contradiction:
Improvestress resistanceVSAvoidbonding process complexity
Core Design Contradiction:
StrengthVSDevice complexity

Solution Approach 1:

The patent applies asymmetry by intentionally misaligning the crystal lattice directions of bonded wafers. Instead of bonding wafers with identical lattice orientations (symmetric approach), the invention bonds wafers with different lattice directions (e.g., <100> with <110>, or <100> with <111>), creating an asymmetric configuration that distributes stress more evenly and prevents warpage and fracture during high-temperature processing.

Inventive Principle:
Principle #4Asymmetry

2Reliability

If wafers are bonded with different lattice directions, then stress resistance is improved, but alignment precision and bonding complexity increase

Engineering Contradiction:
Improvestructural integrityVSAvoidalignment precision
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent applies preliminary action by pre-establishing lattice direction markers and alignment references on the wafers before bonding. The method includes preparing the wafers with known lattice orientations, determining the appropriate angular offset (greater than 0.5 degrees) in advance, and using these pre-determined parameters to guide the bonding alignment process, thereby achieving both high reliability and manufacturing precision.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12543593B2Semiconductor package including semiconductor dies having different lattice directions and method of forming the same
Publication Date: 2026.02.03 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12543593B2 patent drawing
  • US12543593B2 patent drawing
  • US12543593B2 patent drawing

AI summary

A semiconductor die stack includes a first semiconductor die having a first lattice direction, and a second semiconductor die bonded to the first semiconductor die and having a second lattice direction different than the first lattice direction.