IC Die Stack Encapsulation for Void-Free Bonding and Low Warpage

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Solution Overview

Problem

Current semiconductor packaging techniques face challenges in miniaturization, wafer warpage, and efficient encapsulation of gaps between integrated circuit dies, particularly in forming stacked semiconductor devices without external forces and voids in encapsulant materials.

Innovation Solution

The method involves forming a die stack by bonding adjacent integrated circuit dies using a single bonding process without external force, creating a dam structure around the die stack to contain underfill material, and applying encapsulant materials to fill gaps and prevent warpage, using a carrier with an adhesive layer that can be easily removed.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional packaging techniques are used to bond semiconductor dies, then manufacturing process complexity increases, but bonding reliability and mechanical connectivity deteriorate due to requiring multiple external forces and complex alignment procedures

Engineering Contradiction:
Improvebonding reliabilityVSAvoidmanufacturing process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent combines multiple bonding operations into a single bonding process that simultaneously bonds multiple dies to the substrate. This merging of operations eliminates the need for sequential external forcing and complex alignment procedures, thereby improving bonding reliability while reducing manufacturing process complexity.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The bonding process is designed to be self-aligning and self-bonding, where the dies automatically position themselves relative to the substrate and to each other during the bonding process. This self-service approach eliminates the need for complex external alignment mechanisms and forcing devices, simplifying the manufacturing process while ensuring reliable bonding.

Inventive Principle:
Principle #25Self-service

2Manufacturing precision

If encapsulant material is applied to fill gaps between dies, then gap-filling efficiency improves, but void formation increases due to trapped air and incomplete filling

Engineering Contradiction:
Improvegap-filling efficiencyVSAvoidvoid-free encapsulation
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The patent applies preliminary actions to the encapsulant material before final application, including vacuum degassing to remove trapped air bubbles and controlled dispensing to ensure complete gap filling. These preliminary actions prevent void formation during the encapsulation process, achieving both high gap-filling efficiency and void-free encapsulation.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The encapsulant material undergoes controlled phase transitions from liquid to gel to solid states during application. The material is applied in a liquid state that allows complete gap filling, then transitions through a gel state that traps no voids, and finally cures to a solid state that provides structural support. This phase transition approach ensures efficient gap filling without void formation.

Inventive Principle:
Principle #36Phase transitions

3Strength

If multiple bonding processes are used to stack dies, then mechanical connectivity improves, but wafer warpage increases due to repeated thermal and mechanical cycling

Engineering Contradiction:
Improvemechanical connectivityVSAvoidwafer stability
Core Design Contradiction:
StrengthVSStability of the object's composition

Solution Approach 1:

The patent merges multiple bonding operations into a single bonding process that simultaneously bonds multiple dies to the substrate. This approach achieves strong mechanical connectivity through multiple bonds while avoiding repeated thermal and mechanical cycling, thereby preventing wafer warpage and maintaining wafer stability.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The bonding process is designed as a continuous operation that bonds all dies in a single uninterrupted process. This continuity eliminates repeated heating and cooling cycles that would cause thermal expansion and contraction, preventing wafer warpage while ensuring strong mechanical connectivity among all bonded dies.

Inventive Principle:
Principle #20Continuity of useful action

4Strength

If external forces are applied during bonding, then bonding pressure and connectivity improve, but die misalignment and mechanical stress increase

Engineering Contradiction:
Improvebonding connectivityVSAvoiddie alignment precision
Core Design Contradiction:
StrengthVSManufacturing precision

Solution Approach 1:

The bonding process is designed to be self-aligning, where the dies automatically position themselves relative to the substrate and to each other during bonding. This self-service approach eliminates the need for external forcing that would cause misalignment, achieving both strong bonding connectivity and precise die alignment simultaneously.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The bonding process creates an equipotential bonding environment where all dies experience uniform bonding conditions and forces. This equipotential approach ensures that no single die is subjected to excessive stress or misalignment, achieving uniform bonding connectivity and precise alignment across all dies in the stack.

Inventive Principle:
Principle #12Equipotentiality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables efficient gap-filling without voids, reduces wafer warpage, and improves the mechanical and electrical connectivity of the die stack, facilitating the formation of compact and reliable integrated circuit packages.

Implementation Method 1

a carrier (101) to which a wafer (105) is bonded by an adhesive layer (103)

Methodology Applied
Scientific EffectAdhesion: Adhesive

Implementation Method 2

performing a bonding process on the die stack, the bonding process mechanically and electrically connecting adjacent integrated circuit dies of the die stack to each other

Methodology Applied
Scientific EffectSoldering: Soldering

Data Source

PatentUS11810831B2Integrated circuit package and method of forming same
Publication Date: 2023.11.07 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11810831B2 patent drawing
  • US11810831B2 patent drawing
  • US11810831B2 patent drawing

AI summary

An integrated circuit package and a method of forming the same are provided. A method includes stacking a plurality of integrated circuit dies on a wafer to form a die stack. A bonding process is performed on the die stack. The bonding process mechanically and electrically connects adjacent integrated circuit dies of the die stack to each other. A dam structure is formed over the wafer. The dam structure surrounds the die stack. A first encapsulant is formed over the wafer and between the die stack and the dam structure. The first encapsulant fills gaps between the adjacent integrated circuit dies of the die stack. A second encapsulant is formed over the wafer. The second encapsulant surrounds the die stack, the first encapsulant and the dam structure.