Die Stack Optical Interposer for High-Speed Data Transport
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Solution Overview
Problem
Modern electronic devices face challenges in achieving high conductivity for ultra-high frequency applications due to the limitations of copper deposition, such as slow deposition rate, inhomogeneity, and diffusion issues, which affect electrical breakdown and wafer stacking complexity.
Innovation Solution
An electronic device with a die stack configuration, including a first die with light emitting units, a second interposer layer with via holes, and a third die with light detecting units, enabling optical communication and using organic light emitting diodes for low power operation, allowing for bi-directional communication and high-speed data transport.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If copper is used to fill via holes for high conductivity, then electrical conductivity is improved, but deposition rate is slow and layer thickness is inhomogeneous
Solution Approach 1:
The patent replaces the electroplating process (electrical/chemical system) with a direct deposition method that achieves copper filling without the slow electroplating process. This substitution enables faster production while maintaining the high conductivity requirement for ultra-high frequency applications.
2Reliability
If copper is used to fill via holes, then electrical conductivity is improved, but copper diffuses into silicon causing electrical breakdown
Solution Approach 1:
The patent introduces a diffusion barrier layer as an intermediary between the copper via holes and the silicon substrate. This barrier layer prevents copper atoms from diffusing into the silicon while allowing the copper to maintain its electrical conductivity function, thus resolving the harmful diffusion effect.
3Productivity
If wafer stacking is performed with multiple dies, then integration density is improved, but processing complexity increases
Solution Approach 1:
The patent performs preliminary alignment and positioning of multiple dies before the stacking process. By pre-preparing the die arrangement and ensuring proper alignment of via holes and conductive layers, the subsequent stacking and bonding processes become simpler and more reliable, reducing overall processing complexity.
4Manufacturing precision
If standard semiconductor manufacturing processes are used for light emitting units, then manufacturing precision is improved, but device functionality is limited
Solution Approach 1:
The patent combines standard semiconductor manufacturing processes with organic light-emitting materials to create hybrid structures. This composite approach allows the use of precise semiconductor fabrication techniques while incorporating the functional advantages of organic materials, such as flexibility and low-cost processing, thereby expanding device functionality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration provides improved optical communication capabilities, reduces power consumption, and enables high-speed data transport up to 100 Tbit/s, offering a cost-effective alternative to copper-filled via holes while maintaining reliability and integration with standard semiconductor processes.
Implementation Method 1
a first die comprising a first array of light emitting units for emitting light
Implementation Method 2
a third die comprising a third array of light detecting units for detecting light from the first array of light emitting units
Implementation Method 3
The light emitting units are implemented as organic light emitting diodes integrated on the first die
Data Source
AI summary
An electronic device comprising at least one die stack having at least a first die (D1) comprising a first array of light emitting units (OLED) for emitting light, a second layer (D2) comprising a second array of via holes (VH) and a third die (D3) comprising a third array of light detecting units (PD) for detecting light from the first array of light emitting units (OELD) is provided. The second layer (D2) is arranged between the first die (D1) and the third die (D3). The first, second and third array are aligned such that light emitted from the first array of light emitting units (OLED) passed through the second array of via holes (VH) and is detected by the third array of light detecting units (PD). The first array of light emitting units and/or the third array of light detecting units are manufactured based on standard semiconductor manufacturing processes.