Die-to-Die Passive Stack Layout for Lower Parasitic Packaging
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Solution Overview
Problem
Current on-chip capacitor and inductor techniques fail to achieve high capacitance and inductance densities required for modern electronic devices, leading to increased size and parasitic effects in circuit modules and boards.
Innovation Solution
The attachment of an auxiliary die with capacitors and/or inductors to a primary die between its terminals forms a multiple IC stack, reducing parasitic capacitance and inductance, enabling higher frequency operation and improved energy transfer in power converters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If on-chip capacitor techniques (MIM, MOM, MOS) are used to integrate capacitors fully with CMOS IC chips, then capacitor integration is achieved, but capacitance density is limited to a few pF/mm2
Solution Approach 1:
The patent transitions from two-dimensional planar capacitors to three-dimensional stacked capacitors by placing capacitor dies above and below the main IC die. This vertical stacking in the third dimension enables capacitance densities measured in micro-Farads per square millimeter, achieving approximately 1,000,000 times greater capacitance than conventional on-chip techniques while maintaining the same footprint area.
Solution Approach 2:
The patent implements a nested structure where capacitor dies are positioned within the vertical space above and below the main IC die. The capacitor dies are electrically connected to the main die through conductive vias that pass through the substrate, creating a nested arrangement where capacitors are embedded in the vertical dimension rather than occupying lateral space.
2Quantity of substance
If discrete capacitors and inductors are mounted on module substrate or PCB to achieve high capacitance and inductance values, then capacitance and inductance requirements are met, but planar area of mounting structure is consumed
Solution Approach 1:
The patent moves passive components from the two-dimensional planar domain to the three-dimensional vertical domain by stacking capacitor and inductor dies above and below the main IC die. This eliminates the need for lateral placement on module substrates or PCBs, thereby freeing up planar area while maintaining high capacitance and inductance values through vertical integration.
Solution Approach 2:
The patent merges active IC components with passive capacitor and inductor components into a single stacked die assembly. By bonding capacitor dies and inductor dies directly to the main IC die through conductive vias, the patent creates an integrated three-dimensional module that combines previously separate active and passive components, eliminating the need for external mounting structures.
3Ease of manufacture
If discrete capacitors and inductors are placed at a distance from packaged IC, then component placement is simplified, but undesirable impedances and parasitic capacitances and inductances increase
Solution Approach 1:
The patent nests capacitor and inductor dies within immediate proximity to the main IC die by stacking them vertically and connecting through conductive vias. This nested arrangement ensures that passive components are positioned as close as possible to their associated active circuits, minimizing parasitic effects while maintaining ease of manufacture through standardized die-stacking processes.
4Quantity of substance
If very large IC dies are used to achieve high capacitance and inductance values using on-chip techniques, then capacitance and inductance requirements are met, but device size increases
Solution Approach 1:
The patent achieves high capacitance and inductance values without increasing die area by stacking passive components in the vertical dimension. Capacitor dies and inductor dies are bonded above and below the main IC die, allowing the system to achieve micro-Farad level capacitance and high inductance values while maintaining a compact footprint suitable for modern portable electronics.
Data Source
AI summary
Integrated circuit (IC) packaging concepts that include the attachment of an auxiliary die to a primary die between the terminals of the primary die. The auxiliary die may include one or more capacitors and/or inductors as well as active circuitry (including, for example, vertical FETs). In some embodiments, more than one auxiliary IC may be attached (directly or indirectly) to a primary IC. Such a multiple IC stack configuration reduces parasitic capacitance and/or inductance compared to conventional side-by-side arrangements, and thus enables higher frequency operation. In power converters, higher operation frequency generally allows a beneficial tradeoff between reducing the capacitance requirement and/or the inductance requirement (if present) for the circuit, and generally improves the energy transfer capability of the power converter.