3D Die Stack Signal Formatting for Even-Odd Parity Awareness
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Solution Overview
Problem
In 3D stacked devices, existing solutions for determining even/odd die positioning in single-inverter repeater implementations are either non-interchangeable or require late-stage programming, leading to delays in signal propagation and limited flexibility in die placement.
Innovation Solution
An asynchronous die parity determination mechanism is implemented, using a die parity path to identify each die as either even or odd, allowing selective inversion of inter-die signals based on die type, enabling rapid and flexible signal processing without pre-configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate even and odd dies are fabricated with hardwired inversion logic, then signal processing correctness is ensured, but die interchangeability is prevented and pre-determination of die position is required
Solution Approach 1:
The patent changes the parameter of die configuration from fixed hardwired logic to dynamically configurable logic controlled by parity bits. Each die includes control logic that reads a parity bit from configuration data to determine whether to invert the signal, allowing the same physical die to function as either even or odd position die depending on the configured parity bit value.
Solution Approach 2:
The patent makes each die universal by enabling it to perform both even and odd position functions through configurable parity bit interpretation. The control logic is designed to handle both cases (even and odd positions) within the same hardware structure, eliminating the need for separate even and odd die variants.
2Adaptability or versatility
If registers or re-programmable elements are used to identify die position, then die interchangeability is facilitated, but signal propagation is delayed until programming completes
Solution Approach 1:
The patent performs die position identification and configuration setup in advance during the initialization phase, storing parity bits in configuration memory before normal operation begins. This preliminary configuration allows the control logic to immediately use the stored parity bits for signal processing without requiring real-time programming or registration during signal propagation.
Solution Approach 2:
The control logic automatically reads and interprets the configured parity bits without requiring external intervention or complex registration processes. The system self-configures by reading the parity bit from configuration data and automatically adjusting its signal inversion behavior, eliminating the need for manual or complex automated registration procedures.
3Speed
If single-inverter repeaters are used, then propagation delay is reduced, but signal logic state inversion occurs between dies requiring parity awareness
Solution Approach 1:
The patent introduces parity bits as an intermediary mechanism that carries position information through the signal path. The control logic uses this intermediary parity bit to mediate between the single-inverter speed advantage and the need for correct signal inversion, allowing the system to maintain high speed while correctly handling logic state variations through configurable interpretation of the parity bit.
Data Source
AI summary
An electronic device includes a die stack having a plurality of die. The die stack includes a die parity path spanning the plurality of die and configured to alternatingly identify each die as a first type or a second type. The die stack further includes an inter-die signal path spanning the plurality of die and configured to propagate an inter-die signal through the plurality of die, wherein the inter-die signal path is configured to invert a logic state of the inter-die signal between each die. Each die of the plurality of die includes signal formatting logic configured to selectively invert a logic state of the inter-die signal before providing it to other circuitry of the die responsive to whether the die is designated as the first type or the second type.