Die Stack Packaging With Reflowable Connectors for Dense I/O
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Solution Overview
Problem
The increasing density of input/output (I/O) pads on integrated circuit dies due to their miniaturization poses challenges in packaging, particularly in achieving higher parallel processing capabilities while maintaining cost-effectiveness, as traditional bonding techniques like hybrid bonding are costly and may not be necessary for low-performance devices.
Innovation Solution
A die stack is formed by bonding integrated circuit dies using reflowable connectors or adhesives in a face-to-face or back-to-face manner, allowing for cost-effective integration and redistribution of I/O pads, which can be particularly advantageous for low-performance devices, and further incorporating passive devices in the packaging process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional hybrid bonding techniques are used to bond integrated circuit dies, then bonding strength and reliability are improved, but manufacturing cost increases significantly
Solution Approach 1:
The patent replaces expensive hybrid bonding techniques with a more economical bonding approach using standard bonding processes and cost-effective interconnect structures. The invention achieves adequate bonding reliability for low-performance devices without incurring the high costs associated with hybrid bonding, effectively using a simpler, cheaper solution that suffices for the application requirements.
Solution Approach 2:
The patent modifies bonding parameters and interconnect design to achieve reliable bonding at lower cost. By adjusting bonding conditions, interconnect geometry, and material selection, the invention attains sufficient bonding strength and electrical connectivity without requiring the advanced hybrid bonding process, thus reducing manufacturing cost while maintaining adequate reliability.
2Productivity
If the density of I/O pads on integrated circuit dies is increased due to miniaturization, then the number of functions integrated is improved, but packaging difficulty increases
Solution Approach 1:
The patent transitions from planar I/O pad arrangements to three-dimensional interconnect structures. By stacking dies vertically and using through-silicon vias (TSVs) and vertical interconnects, the invention redistributes I/O pads across multiple layers and dimensions, effectively increasing integration density while managing packaging complexity through spatial reorganization.
Solution Approach 2:
The patent implements nested interconnect structures where multiple interconnect layers and redistribution layers are stacked within the package. The I/O pads are nested across multiple die layers and interconnect levels, allowing high-density I/O integration by utilizing vertical space and hierarchical interconnect architectures rather than spreading pads across a larger planar area.
3Ease of manufacture
If reflowable connectors or adhesives are used instead of hybrid bonding for die stacking, then manufacturing cost is reduced, but bonding precision and fine pitch capability may be compromised
Solution Approach 1:
The patent optimizes bonding parameters including temperature profiles, pressure conditions, and reflow characteristics to achieve adequate bonding precision using standard reflowable connectors or adhesives. By carefully controlling bonding parameters and designing interconnect structures with appropriate tolerances, the invention attains sufficient alignment accuracy without requiring the superior precision of hybrid bonding, thus reducing manufacturing cost.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables cost-effective die stacking with potential for increased I/O connector counts and finer pitches without the need for expensive hybrid bonding, making it suitable for low-performance devices while allowing for the integration of passive devices in the packaging process.
Implementation Method 1
bonding integrated circuit dies using reflowable connectors or adhesives
Implementation Method 2
bonding integrated circuit dies using reflowable connectors
Data Source
AI summary
In an embodiment, a structure includes: a first integrated circuit die including first die connectors; a first dielectric layer on the first die connectors; first conductive vias extending through the first dielectric layer, the first conductive vias connected to a first subset of the first die connectors; a second integrated circuit die bonded to a second subset of the first die connectors with first reflowable connectors; a first encapsulant surrounding the second integrated circuit die and the first conductive vias, the first encapsulant and the first integrated circuit die being laterally coterminous; second conductive vias adjacent the first integrated circuit die; a second encapsulant surrounding the second conductive vias, the first encapsulant, and the first integrated circuit die; and a first redistribution structure including first redistribution lines, the first redistribution lines connected to the first conductive vias and the second conductive vias.