3D Die Stack Sensor Network for Physical Tamper Detection
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Solution Overview
Problem
Integrated circuit die stacks face challenges in detecting physical tampering attempts, such as laser attacks and focused ion beam attacks, which require physical access and are exacerbated by thinner substrates and active-on-active stacked die architectures, necessitating improved security measures.
Innovation Solution
An integrated circuit die stack with a sensor network extending across its top surface, utilizing addressable memories and through-silicon-vias to detect tampering events by analyzing sensing signals from a probing signal, allowing for tamper detection and location identification without substantial manufacturing cost increases or functional delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If physical attacks are performed with backside access using laser or focused ion beam, then access to internal data and algorithms can be gained, but security of the integrated circuit die stack is compromised
Solution Approach 1:
The patent implements a sensor network that is pre-deployed across the top surface of the first integrated circuit die before any tampering can occur. This sensor network, coupled with through-silicon-vias to a detection die, creates a preliminary detection system that can identify physical attacks (laser, focused ion beam, or other tampering) before they can compromise the security of the die stack. The sensor network is activated and monitored continuously, enabling early detection and response to physical threats.
2Productivity
If thinner substrates and active-on-active stacked die architectures are used, then processing capabilities are increased, but vulnerability to physical attacks is exacerbated
Solution Approach 1:
The patent introduces a sensor network as an intermediary layer between the thin substrate/die stack and the external environment. This sensor network, distributed across the top surface of the first integrated circuit die, acts as a protective mediator that detects physical attacks (laser, focused ion beam, or other tampering) before they can reach and compromise the vulnerable thin substrate and active-on-active stacked die architectures. The sensor network translates physical threats into detectable signals without interfering with the normal high-speed processing functions of the thin substrate.
3Reliability
If a sensor network is implemented across the top surface of the first integrated circuit die, then tamper detection capability is improved, but device complexity increases
Solution Approach 1:
The patent employs addressable memory cells within the sensor network that serve multiple functions: they act as sensors for detecting physical tampering, store configuration data, and provide addressable access for selective reading. This multi-functionality reduces overall device complexity by consolidating what would otherwise require separate components into a single integrated structure. The same memory infrastructure that stores data can also serve as the sensing element, eliminating the need for dedicated sensor hardware in each location.
Solution Approach 2:
The patent utilizes the addressable nature of memory cells to dynamically change the operational parameters of the sensor network. By selectively addressing different memory cells, the system can activate or deactivate specific sensing regions, adjust sensitivity thresholds, or reconfigure the detection pattern without physical changes to the hardware. This parameter-based control simplifies the device architecture by using software/firmware control rather than complex hardware switching networks.
Data Source
AI summary
An integrated circuit die stack and method thereof are described herein that is capable of detecting a physical tampering event. The integrated circuit die stack includes a first integrated circuit die including a sensor network that extends substantially across an entire top surface of the first integrated circuit die, and a second integrated circuit die stacked below the first integrated circuit die. The second integrated circuit die is configured to receive sensing signals generated by the sensor network via a plurality of through-silicon-vias coupled with the first integrated circuit die and the second integrated circuit die.