Die Stack Test Circuits Reducing Pad Area and RC Delays

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Solution Overview

Problem

Taller and more complex die stacks face challenges with area consumption for externally accessible pads and increased RC parasitic delays and IR voltage drops, making testing more problematic.

Innovation Solution

Implementing wafer-level test circuits configured in a daisy chain and local die-level testing to reduce area consumption and mitigate RC parasitic delays and IR voltage drops, with test data-input and output paths extending through each level of the die stack.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multiple arrays of externally accessible pads are provided at the exit level of die stacks, then testing capability is improved, but area consumption increases significantly

Engineering Contradiction:

Improvetesting capabilityVSAvoidarea consumption

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

Multiple test data-out pads are merged into a single shared test data-out pad at the exit level. The patent connects test data-out pads from different die levels to a common pad, reducing the number of externally accessible pads while maintaining testing capability for all dies in the stack.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent introduces vertical dimensionality by routing test signals through intermediate levels of the die stack. Instead of providing separate pads at the exit level for each die, test signals traverse through multiple die levels vertically, allowing testing of internal dies without additional external pads.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Adaptability or versatility

If die stacks are made taller and more complex, then functionality is improved, but RC parasitic delays and IR voltage drops increase

Engineering Contradiction:

ImprovefunctionalityVSAvoidRC parasitic delays and IR voltage drops

Core Design Contradiction:

Adaptability or versatilityVSObject-affected harmful factors

Solution Approach 1:

The test circuit is segmented into multiple levels corresponding to different die in the stack. Each die level has its own test circuit with separate test data-in and test data-out pads, allowing localized testing that reduces signal path length and mitigates RC delays and IR drops across the entire stack.

Inventive Principle:

Principle #1Segmentation

3Reliability

If multiple arrays of externally accessible pads are provided for testing, then testing coverage is improved, but device complexity increases

Engineering Contradiction:

Improvetesting coverageVSAvoiddevice complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The shared test data-out pad serves multiple functions by receiving test data outputs from multiple different die levels. This single pad provides universal access point for testing all dies in the stack, reducing device complexity while maintaining comprehensive testing coverage.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS11054461B1Test circuits for testing a die stack

Publication Date: 2021.07.06 XILINX INC

AI summary

Device(s) and method(s) related generally to a wafer or die stack are disclosed. In one such device, a die stack of two or more integrated circuit dies has associated therewith test circuits corresponding to each level of the die stack each with a set of pads. A test data-input path includes being from: a test data-in pad through a test circuit to a test data-out pad of each of the test circuits; and the test data-out pad to the test data-in pad between consecutive levels of the test circuits. Each of the set of pads includes the test data-in pad and the test data-out pad respectively thereof. A test data-output path is coupled to the test data-out pad of a level of the levels.