3D Semiconductor Die Stack With Thermal Silicon Substrates
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Solution Overview
Problem
Three-dimensional integrated circuit (3DIC) solutions face challenges in thermal management, power delivery, and yield due to the complexity of integrating heterogeneous chip sizes and functionalities in compact systems, which affects their performance in high-performance computing, AI, 5G, and edge computing applications.
Innovation Solution
The integration of semiconductor wafers with thermal silicon substrates and a patterned dielectric filling material, along with a redistribution circuit structure and bonding structures, to create a compact and efficient SoIC structure that addresses thermal management and yield issues while enabling miniaturized and highly integrated heterogeneous integration systems.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If heterogeneous chips with different sizes and functionalities are integrated into a compact system, then packaging density and functionality are improved, but thermal management and yield become more difficult to control
Solution Approach 1:
The patent segments the integration process into multiple stages: first integrating chips of the same size and functionality to achieve high yield, then separately integrating chips with different sizes and functionalities. This staged segmentation approach maintains yield while achieving heterogeneous integration capability.
Solution Approach 2:
The patent introduces an intermediary carrier substrate that facilitates the integration of heterogeneous chips. This intermediary platform enables different chip sizes and functionalities to be integrated without directly compromising yield, as the carrier substrate provides a controlled integration environment.
2Area of stationary object
If chips are integrated into a compact system, then packaging density is improved, but thermal dissipation becomes more challenging
Solution Approach 1:
The patent transitions from two-dimensional planar integration to three-dimensional vertical stacking, allowing chips to be arranged in multiple layers. This dimensional change enables compact packaging while providing multiple pathways for thermal dissipation through the vertical structure and intermediate substrates.
Solution Approach 2:
The carrier substrate acts as a thermal intermediary between different chip layers, providing thermal management pathways that enable efficient heat dissipation while maintaining compact packaging density.
3Adaptability or versatility
If heterogeneous integration is implemented, then functionality and computing efficiency are improved, but device complexity increases
Solution Approach 1:
The patent segments heterogeneous integration into standardized modules that can be independently fabricated and tested before final assembly. This segmentation reduces integration complexity by breaking down the complex heterogeneous integration process into manageable, standardized steps.
Solution Approach 2:
The patent develops universal carrier substrates and interconnection standards that can accommodate different chip types and sizes. This universality simplifies the integration process by providing a common platform for heterogeneous chips, reducing the complexity of custom integration for each chip combination.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances thermal dissipation, signal transmission, and reliability, improving the performance and yield of SoIC structures for advanced computing applications by providing effective heat dissipation and electromagnetic interference shielding.
Implementation Method 1
thermal silicon substrates disposed on the first semiconductor die, wherein the thermal silicon substrates are spaced apart from the second semiconductor die
Implementation Method 2
the filling material layer is spaced apart from the second semiconductor die and the thermal silicon substrates by the insulator, wherein the ratio of a height of the second semiconductor die to a minimum distance between the second semiconductor die and the thermal silicon substrates ranges from about 0.015 to about 20
Data Source
AI summary
A semiconductor device including a first semiconductor die, a second semiconductor die, thermal silicon substrates and an encapsulation is provided. The second semiconductor die is disposed on and electrically connected to the first semiconductor die. The thermal silicon substrates are disposed on the first semiconductor die, wherein the thermal silicon substrates are spaced apart from the second semiconductor die. The encapsulation is disposed on the first semiconductor die. The encapsulation encapsulates the second semiconductor die and the thermal silicon substrates. The encapsulation includes a filling material layer and an insulator, wherein the filling material layer is disposed on the first semiconductor die and located between the second semiconductor die and thermal silicon substrates, and the filling material layer is spaced apart from the second semiconductor die and the thermal silicon substrates by the insulator.