Die Stack Interconnect Structure to Cut TSV Parasitic Capacitance
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Solution Overview
Problem
In High-Performance Computing (HPC) systems, the formation of Through-Silicon Vias (TSVs) in memory dies for connecting to logic dies leads to parasitic capacitance, causing signal attenuation due to loading effects, which existing methods fail to adequately address.
Innovation Solution
The formation of through-dielectric vias in the encapsulant material instead of the semiconductor substrates eliminates parasitic capacitance by using redistribution structures and dielectric layers to connect memory dies to logic dies, avoiding signal attenuation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Through-Silicon Vias (TSVs) are formed in memory dies to connect to logic dies, then electrical connections between memory and logic dies are established, but parasitic capacitance causes signal attenuation
Solution Approach 1:
The patent introduces an intermediary structure (encapsulant with through-encapsulant vias) between the memory die and logic die to eliminate direct TSV formation in the semiconductor substrate. This mediator avoids parasitic capacitance while maintaining electrical connectivity through alternative pathways using redistribution layers and metal interconnects.
Solution Approach 2:
The patent segments the electrical connection path by separating the vertical through-substrate vias into horizontal redistribution layers and vertical via connections. This segmentation allows the signal to travel through dielectric materials rather than directly through the semiconductor substrate, reducing parasitic capacitance effects.
2Reliability
If TSVs are formed in memory dies, then electrical connectivity is achieved, but signal attenuation occurs due to loading effects
Solution Approach 1:
The encapsulant material serves as an intermediary that provides a low-parasitic-pathway for signal transmission. Through-encapsulant vias conduct signals through the encapsulant rather than through the semiconductor substrate, minimizing loading effects and signal attenuation.
Solution Approach 2:
The patent changes the physical parameters of the connection path by using dielectric materials with different electrical characteristics than semiconductor substrates. This parameter change reduces parasitic capacitance and improves signal integrity.
3Reliability
If conventional TSV methods are used, then memory dies are connected to logic dies, but parasitic capacitance and signal attenuation cannot be adequately addressed
Solution Approach 1:
The patent merges the encapsulation function with the electrical interconnection function by forming through-encapsulant vias during the encapsulation process. This integration eliminates the need for separate TSV formation steps and reduces overall device complexity while maintaining connection reliability.
Solution Approach 2:
The patent performs preliminary actions by forming the encapsulant and through-encapsulant vias before final die stacking. This preliminary preparation simplifies subsequent bonding processes and ensures reliable electrical connections are established before the dies are permanently assembled.
Data Source
AI summary
A method includes thinning a semiconductor substrate of a device die to reveal through-substrate vias that extend into the semiconductor substrate, and forming a first redistribution structure, which includes forming a first plurality of dielectric layers over the semiconductor substrate, and forming a first plurality of redistribution lines in the first plurality of dielectric layers. The first plurality of redistribution lines are electrically connected to the through-substrate vias. The method further includes placing a first memory die over the first redistribution structure, and forming a first plurality of metal posts over the first redistribution structure. The first plurality of metal posts are electrically connected to the first plurality of redistribution lines. The first memory die is encapsulated in a first encapsulant. A second plurality of redistribution lines are formed over, and electrically connected to, the first plurality of metal posts and the first memory die.