Die Stack Bonding Structure for Precise Via Pad Alignment
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor devices become smaller, accurately positioning electrical connecting pads becomes increasingly difficult, affecting conductive performance.
Innovation Solution
A semiconductor device design featuring a heat dissipation unit with composite vias and conductive plates, including first and second through semiconductor vias, surrounded by protection layers, and connected via conductive connecting portions to ensure precise placement and improved conductivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If semiconductor devices are miniaturized to reduce size and increase integration, then device functionality and integration density are improved, but positioning precision of electrical connecting pads deteriorates
Solution Approach 1:
The patent introduces an intermediary alignment structure consisting of alignment marks and reference features that mediate between the miniaturized device components and the positioning system. These alignment features serve as intermediate reference points that enable precise positioning of electrical connecting pads even as device dimensions are reduced, resolving the contradiction between miniaturization and positioning precision
Solution Approach 2:
The patent implements preliminary alignment actions by pre-defining alignment marks and reference structures before the actual pad positioning process. This preliminary establishment of reference frameworks enables subsequent precise positioning operations, allowing the device to maintain manufacturing precision despite miniaturization
2Reliability
If conventional through semiconductor via structures are used to reduce electrical resistance, then conduction efficiency is improved, but positioning accuracy of electrical connecting pads deteriorates
Solution Approach 1:
The patent segments the via structure into distinct functional components: alignment marks, reference features, and conductive via portions. This segmentation allows the alignment functionality to be separated from the conduction functionality, enabling precise positioning through the alignment features while maintaining excellent conductive performance through the optimized via structure
Solution Approach 2:
The patent applies local quality by giving different portions of the via structure different functions: certain regions contain alignment marks with specific geometric properties for positioning, while other regions are optimized for electrical conduction. This localized functional differentiation resolves the contradiction between positioning accuracy and conductive performance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design allows for precise positioning of conductive connecting portions, enhancing conductive performance and reducing electrical resistance.
Implementation Method 1
The carrier structure includes a heat dissipation unit configured to transfer heat generated from the die stack
Data Source
AI summary
The present disclosure provides a semiconductor device. The semiconductor device includes a die stack, an intervening bonding layer, and a carrier structure. The intervening bonding layer is positioned on the die stack. The carrier structure is disposed on the intervening bonding layer opposite to the die stack. The carrier structure includes a heat dissipation unit configured to transfer heat generated from the die stack. The heat dissipation unit includes composite vias and conductive plates. Each of the composite vias includes a first through semiconductor via and a second through semiconductor via. The conductive plates are couple to the composite vias.