Die Stack Via Layout for Faster Bus Signaling
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Solution Overview
Problem
As the number of integrated circuit dies increases in a stack, existing methods for connecting signal lines through vias lead to reduced signal quality and bus speeds due to increased loading on buses, making it difficult to maintain efficient communication between chips.
Innovation Solution
The use of translationally compatible pass-through vias (PTVs) and through-silicon vias (TSVs) on identical dies, where PTVs in one die align with TSVs in another, allowing for efficient signal transmission from a substrate through the die stack without additional external wiring, and optionally incorporating an interface die to simplify substrate design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple integrated circuit dies are stacked to increase packaging density, then the quantity of circuits in confined space is improved, but the bus loading increases reducing signal quality and bus speeds
Solution Approach 1:
The patent segments the signal transmission path by introducing intermediate redistribution layers between dies that break up long bus lines into shorter segments. Each die connects to adjacent dies through localized interconnects rather than long vertical buses, reducing capacitive loading and signal degradation while maintaining high circuit density in the stacked configuration.
Solution Approach 2:
The patent transitions from traditional planar bus architectures to a three-dimensional stacked architecture with redistribution layers. Signal paths are redistributed across multiple horizontal planes (redistribution layers) between vertical die stacks, effectively moving signal transmission from a two-dimensional bus structure to a three-dimensional network that reduces loading on any single signal path.
2Quantity of substance
If multiple integrated circuit dies are stacked to increase packaging density, then the quantity of circuits in confined space is improved, but bus speeds are reduced due to increased loading
Solution Approach 1:
The patent segments the bus structure into multiple shorter interconnect paths through redistribution layers. Instead of single long vertical buses spanning all dies, signals travel through shorter horizontal and vertical segments, reducing RC delays and maintaining higher transmission speeds while accommodating more dies in the stack.
Solution Approach 2:
The redistribution layers act as intermediary structures between dies, providing localized signal routing and impedance matching. These intermediate layers buffer the signal transitions between dies, reducing reflection and loading effects that would otherwise slow down bus operations in densely stacked configurations.
3Ease of operation
If signal lines are wrapped outside the dies or redistribution layers are placed between dies, then connectivity between dies is achieved, but device complexity increases
Solution Approach 1:
The patent merges the redistribution function with the interconnect structure itself. The redistribution layers are integrated into the stacking process and formed using the same semiconductor fabrication techniques as the dies, combining multiple functions (signal routing, impedance matching, and mechanical support) into a single integrated structure rather than adding separate external wiring layers.
Solution Approach 2:
The redistribution layers serve multiple functions simultaneously: they provide signal routing between dies, establish electrical references and grounds, provide mechanical support between dies, and enable impedance matching. This multi-functionality reduces the need for additional specialized structures that would increase device complexity.
Data Source
AI summary
An integrated circuit die stack including a first integrated circuit die mounted upon a substrate, the first die including pass-through vias (‘PTVs’) composed of conductive pathways through the first die with no connection to any circuitry on the first die; and a second integrated circuit die, identical to the first die, shifted in position with respect to the first die and mounted upon the first die, with the PTVs in the first die connecting signal lines from the substrate through the first die to through silicon vias (‘TSVs’) in the second die composed of conductive pathways through the second die connected to electronic circuitry on the second die; with the TSVs and PTVs disposed upon each identical die so that the positions of the TSVs and PTVs on each identical die are translationally compatible with respect to the TSVs and PTVs on the other identical die.