Semiconductor Package Layout With Direct BEOL Bonding Without Interposers
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Solution Overview
Problem
The increasing integration density of semiconductor components poses challenges in connecting integrated circuit dies effectively through interposers alone, leading to difficulties in communication and packaging efficiency.
Innovation Solution
The implementation of direct BEOL-BEOL bonding between integrated circuit dies, along with the use of a substrate for direct connection to a printed circuit board, eliminates the need for interposers and redistribution layers, enabling heterogeneous integration and shorter communication distances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If interposers are used to connect integrated circuit dies, then communication between dies is enabled, but manufacturing complexity and cost increase
Solution Approach 1:
The patent removes the interposer from the packaging structure, eliminating the intermediate substrate that previously enabled die-to-die communication. Instead, dies are directly bonded together through hybrid bonding techniques, extracting the unnecessary intermediary component while maintaining connectivity functionality.
Solution Approach 2:
The patent merges the functions of multiple separate components (interposer, redistribution layers, bonding pads) into a direct die-to-die bonding interface. By integrating the interconnect structures directly onto the die surfaces and bonding them together, the system combines previously separate elements into a unified direct connection architecture.
2Ease of operation
If interposers and redistribution layers are used, then input/output communication is achieved, but manufacturing cost increases
Solution Approach 1:
The patent extracts and eliminates the interposer and redistribution layers from the packaging architecture. By removing these expensive intermediary components, the system achieves I/O communication through direct die bonding, significantly reducing material costs and manufacturing complexity.
Solution Approach 2:
Instead of using the conventional approach of adding intermediary layers (interposer, redistribution layers) to achieve connectivity, the patent inverts the approach by directly bonding die surfaces together. This inversion eliminates the need for additional costly layers while maintaining or improving communication efficiency.
3Strength
If thick copper or plastic materials are used in packaging, then structural strength is provided, but thermal management performance deteriorates
Solution Approach 1:
The patent changes the material parameters by replacing thick copper or plastic packaging materials with thin-film interconnect structures and alternative substrate materials. This parameter change maintains structural integrity while improving thermal conductivity, allowing heat to dissipate more effectively from the die surfaces.
Solution Approach 2:
The patent employs composite material structures combining organic and inorganic substrates with thin-film metal interconnects. This composite approach provides sufficient structural strength while enabling superior thermal management compared to traditional thick copper or plastic packaging materials.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces manufacturing costs, enhances performance, and facilitates better thermal management by eliminating thick copper or plastic materials, allowing for improved heat dissipation and mechanical strength.
Implementation Method 1
heating the first and second integrated circuit dies to a temperature so that the metal portions are interconnected by metal inter-diffusion
Data Source
AI summary
Embodiments of the present disclosure provide a semiconductor package. In one embodiment, the semiconductor package includes a first integrated circuit die having a first circuit design, and the first integrated circuit die comprises a first device layer and a first interconnect structure. The semiconductor package also includes a second integrated circuit die having a second circuit design different than the first circuit design, and the second integrated circuit die comprises a second device layer and a second interconnect structure having a first side in contact with the first device layer and a second side in direct contact with the first interconnect structure of the first integrated circuit die. The semiconductor package further includes a substrate having a first side bonded to the first interconnect structure, wherein the second integrated circuit die is surrounded by at least a portion of the substrate.