3D Die-Stacked Microelectronic Assembly for Dense Interconnects
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Solution Overview
Problem
The challenge in microelectronic assemblies is to efficiently communicate large numbers of signals between multiple integrated circuit (IC) dies while addressing thermal constraints, power delivery limitations, and the increasing miniaturization of dies, which conventional approaches struggle to achieve with reliable attachment, cost-effectiveness, power efficiency, and design flexibility.
Innovation Solution
The implementation of a microelectronic assembly design that includes a package substrate coupled to IC dies via die-to-package substrate interconnects and die-to-die interconnects, allowing for improved power delivery and signal speed while reducing package size, using conductive pathways and interconnects with varying pitches to facilitate communication between dies, and incorporating a composite die structure for enhanced thermal management and mechanical stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional substrates are used to couple integrated circuit dies, then mechanical stability is achieved, but interconnect pitch is constrained by manufacturing, materials, and thermal considerations
Solution Approach 1:
The patent transitions from planar substrate-based interconnection to three-dimensional die stacking with vertical interconnects. Multiple IC dies are coupled face-to-face in a vertical arrangement, enabling interconnect pitches that are not constrained by conventional substrate manufacturing capabilities. The vertical dimension provides additional routing space and allows for higher density interconnections.
Solution Approach 2:
The patent introduces intermediate coupling structures including conductive bumps, solder joints, and interface layers that facilitate direct die-to-die bonding. These intermediaries enable precise alignment and electrical connection between dies without requiring conventional substrate trace routing, thereby achieving finer interconnect pitches.
2Productivity
If multiple IC dies are coupled together, then signal communication between dies is enabled, but thermal management becomes more challenging
Solution Approach 1:
The patent incorporates thermal interface materials and heat dissipation structures at the die-to-die interfaces. These intermediate layers facilitate heat transfer between stacked dies and to the underlying substrate, managing thermal accumulation in high-density multi-die configurations.
Solution Approach 2:
The coupling structures serve dual functions: electrical interconnection and thermal management. The same interface layers and conductive structures that enable signal communication between dies also provide thermal pathways for heat dissipation, reducing the need for separate thermal management components.
3Area of moving object
If die size is reduced for miniaturization, then device density increases, but power delivery limitations become more significant
Solution Approach 1:
The patent moves power delivery from lateral routing on small dies to vertical routing through stacked dies. Power and ground connections are established through vertical interconnects at die interfaces, providing dedicated power pathways that are not constrained by the reduced lateral die area. This enables adequate power delivery even as die dimensions shrink.
Solution Approach 2:
The patent divides the system into multiple functional dies stacked vertically, with dedicated power delivery dies and signal processing dies. This segmentation allows power delivery functions to be optimized separately from signal processing, with thick copper layers and wide power vias in dedicated power layers that do not consume signal routing space on active computation dies.
4Reliability
If conventional attachment methods are used, then mechanical stability is achieved, but design flexibility is limited
Solution Approach 1:
The patent employs reconfigurable interconnect structures and programmable logic devices that allow the functional connectivity between dies to be dynamically adjusted. This enables the same physical die stack to be reconfigured for different applications and design requirements while maintaining robust mechanical attachment through standardized bonding interfaces.
Data Source
AI summary
Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include: a first die having a first surface and an opposing second surface, first conductive contacts at the first surface of the first die, and second conductive contacts at the second surface of the first die; and a second die having a first surface and an opposing second surface, and first conductive contacts at the first surface of the second die; wherein the second conductive contacts of the first die are coupled to the first conductive contacts of the second die by interconnects, the second surface of the first die is between the first surface of the first die and the first surface of the second die, and a footprint of the first die is smaller than and contained within a footprint of the second die.