Vertical Semiconductor Die Stacking with Bond Pad Porch
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Solution Overview
Problem
Current semiconductor die stacking methods, such as shingle stacking, increase the footprint of semiconductor packages and are costly due to the use of through-substrate vias (TSVs), while existing vertical stacking techniques face challenges in optimizing the fabrication processes for CMOS and memory cell regions independently.
Innovation Solution
The approach involves fabricating CMOS and memory cell regions as separate semiconductor dies, vertically stacking them to reduce the distance between CMOS circuitry and memory cells, and using conductive components like copper to couple them, allowing for reduced footprint and improved performance by creating a porch for bond pad access without increasing the overall footprint, thus avoiding shingle stacking and providing a lower-cost alternative to TSVs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If shingle stacking is used to stack semiconductor dies, then the footprint of the semiconductor package increases, but the bond pads become more accessible
Solution Approach 1:
The patent transitions from lateral shingle stacking to vertical stacking by utilizing the third dimension (height). Multiple semiconductor dies are stacked vertically one on top of another, with bond pads accessible from the sides of the stack rather than requiring lateral offset arrangements. This dimensional change resolves the contradiction by maintaining bond pad accessibility while minimizing footprint.
2Adaptability or versatility
If through-substrate vias (TSVs) are used to facilitate die stacking, then the stacking capability is improved, but the manufacturing cost increases
Solution Approach 1:
The patent replaces expensive TSV technology with wire bonding, which uses simpler, less costly interconnect structures. Instead of forming complex through-substrate vias that require precise alignment and expensive manufacturing processes, the invention uses wire bonds that can be formed more economically while achieving the same electrical interconnection function between stacked dies.
3Area of stationary object
If vertical stacking is used to reduce footprint, then the distance between CMOS circuitry and memory cells is reduced, but fabrication process optimization becomes more difficult
Solution Approach 1:
The patent divides the semiconductor device into separate functional segments (CMOS die and memory cell die) that are fabricated independently using optimized processes for each function, then stacked vertically. This segmentation allows each die to be manufactured with process parameters optimized for its specific function, avoiding the complexity of trying to optimize a single monolithic structure for multiple functions.
Data Source
AI summary
Semiconductor die stacks, and associated methods and systems are disclosed. The semiconductor die stack may include a first die with a memory array and a second die with CMOS circuitry configured to access the memory array. The first die may not have circuitry for accessing the memory array. Further, the first and second dies may be bonded to function as a single memory device, and front surfaces of the first and second dies are conjoined to form electrical connections therebetween. The second die may include a portion uncovered by the first die, where bond pads of the semiconductor die stack are located. The first die may provide a space for bond wires to connect to the bond pads without interfering with another die attached above the semiconductor die stack. Multiple semiconductor die stacks may be stacked on top of and in line with each other.