Die Stacking C2C Interface Redundancy Without Throughput Loss
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Solution Overview
Problem
Large die stacking platforms experience platform failure or limited performance due to single C2C input/output (I/O) issues, which can be mechanical, electrical, or due to silicon defects, and existing solutions for C2C I/O failure or limited performance result in tradeoffs between throughput and yield.
Innovation Solution
A die configuration on a substrate where integrated circuits are disposed with redundant C2C interfaces, allowing only one interface to be active at a time, enabling high platform yield and performance by switching to redundant interfaces when failures occur.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If redundant C2C interfaces are added to each die, then platform yield is improved, but overall throughput is lowered
Solution Approach 1:
The system segments the C2C interface resources by creating separate physical terminal connections for first and second integrated circuits. Each circuit has its own dedicated C2C interface that can operate independently, allowing redundancy without forcing shared resources that would reduce throughput.
Solution Approach 2:
A switch component acts as an intermediary between the first and second integrated circuits and the physical terminal. The switch enables selective connection of either circuit to the terminal based on operational needs, allowing redundant interfaces to coexist without interfering with each other's throughput performance.
2Reliability
If C2C I/O calibration is performed periodically, then performance is improved, but calibration time is excessive or continuous operation is interrupted
Solution Approach 1:
The system implements periodic calibration of C2C I/O interfaces during normal operation using calibration patterns transmitted through the serial communication links. This allows performance optimization to occur at regular intervals without requiring system shutdown or extended downtime.
Solution Approach 2:
The calibration process is designed to occur continuously during normal data transmission operations. Calibration patterns are interleaved with data traffic, allowing the C2C interfaces to maintain optimal performance while the system remains fully operational and productive throughout the calibration process.
Data Source
AI summary
Technologies for chip-to-chip (C2C) yield and performance optimization in a die stacking platform are described. One apparatus includes a substrate, a first integrated circuit disposed on the substrate at a first location, a second integrated circuit disposed on the substrate at a second location, and a third integrated circuit disposed on the second integrated circuit. The second integrated circuit is coupled to the first integrated circuit using a first chip-to-chip (C2C) interface via a physical terminal. The third integrated circuit is coupled to the first integrated circuit using a second C2C interface via the physical terminal. Only one of the first C2C interface and the second C2C interface is active at a time.