Die Stacking Structure with Direct Interconnect via Probe Pads
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Solution Overview
Problem
Current semiconductor packaging technologies face challenges in achieving high integration density and efficient die stacking while minimizing device size and cost, particularly in the formation of die stacks with through-vias and redistribution lines, which affect the integration and testing of semiconductor devices.
Innovation Solution
A die stacking process involving the bonding of device dies with through-vias and redistribution lines formed without solder regions, using a fan-out process to connect the redistribution lines directly to the second device die, and encapsulating the first device die with an encapsulant that contacts the probe pads, allowing for efficient probing and bonding without the need for solder regions between the interconnect structure and the die stack.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If solder regions are used to connect the interconnect structure to the die stack, then electrical connection is achieved, but the complexity of semiconductor packaging increases and manufacturing yield decreases
Solution Approach 1:
The patent removes solder regions from the packaging structure entirely. The interconnect structure is designed to contact the die stack directly through probe pads without requiring solder joints, thereby eliminating the complexity and reliability issues associated with soldering processes while maintaining electrical connectivity.
Solution Approach 2:
The patent introduces probe pads as an intermediary structure on the die stack surface that enables direct electrical contact with the interconnect structure. These probe pads serve as the mediating element that facilitates electrical connection without requiring solder regions, simplifying the overall packaging architecture.
2Quantity of substance
If through-vias and redistribution lines are formed in the die stack, then integration density is improved, but the manufacturing process complexity increases
Solution Approach 1:
The patent forms through-vias and redistribution lines within the die stack during the semiconductor fabrication process before the packaging stage. This preliminary formation of interconnect structures allows for high integration density to be achieved within the die itself, reducing the need for complex post-packaging interconnection processes.
3Productivity
If the encapsulant contacts the probe pads, then probing and testing become more efficient, but the structural complexity of the package increases
Solution Approach 1:
The patent designs the encapsulant structure to automatically contact and protect the probe pads during the encapsulation process. The encapsulant material is applied in a manner that naturally conforms to and contacts the probe pad structures, enabling efficient probing and testing without requiring additional structural elements or complex alignment processes.
Data Source
AI summary
A method includes bonding a first device die to a second device die, encapsulating the first device die in a first encapsulant, performing a backside grinding process on the second device die to reveal through-vias in the second device die, and forming first electrical connectors on the second device die to form a package. The package includes the first device die and the second device die. The method further includes encapsulating the first package in a second encapsulant, and forming an interconnect structure overlapping the first package and the second encapsulant. The interconnect structure comprises second electrical connectors.