Hybrid-Bonded Die Stacking with Selective Si Thinning
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Solution Overview
Problem
Conventional multi-layer die stacking in memory applications is limited by the vertical height of conductive bumps and underfill processes, restricting the number of stacks that can be formed while maintaining a maximum form factor.
Innovation Solution
The method involves direct hybrid bonding of dies to a substrate without conductive bumps and underfill, using selective silicon thinning, passivation, and filling gaps with a fill material to form conductive vias, reducing the vertical height of each die layer and enabling more stacks within a fixed form factor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional flip-chip approach with conductive bumps and underfill is used, then electrical connection and stress relief are provided, but the vertical height increases which restricts the number of stacks
Solution Approach 1:
The patent removes the conductive bumps and underfill from the conventional flip-chip approach, extracting only the essential functions needed. The solder bumps are eliminated entirely, and the underfill is replaced with a different structural approach using vias and interlayer dielectric material, thereby reducing vertical height while maintaining electrical connection functionality.
Solution Approach 2:
The patent transitions from a vertical stacking approach with height-consuming components to a planar integration approach where electrical connections are established through vias within the same or adjacent layers. The conductive paths are routed through the interlayer dielectric and via structures rather than extending vertically through thick underfill and bump assemblies, effectively moving the connection strategy to a different dimensional approach.
2Length of moving object
If hybrid bonding process is used to bond dies directly to substrate, then vertical height is reduced, but new manufacturing processes are required
Solution Approach 1:
The manufacturing process is divided into distinct sequential steps: bonding dies to substrate, performing selective silicon thinning, forming vias through the thinned dies, filling gaps with interlayer dielectric material, and planarization. This segmentation allows each process to be optimized and controlled independently, making the complex hybrid bonding process more manageable and manufacturable.
Solution Approach 2:
The patent performs selective silicon thinning on the dies before final assembly and bonding. By removing excess silicon thickness in advance, the subsequent via formation and gap filling processes become more efficient, and the overall structure achieves the desired low profile without requiring complex post-bonding thickness control mechanisms.
3Length of moving object
If selective silicon thinning is performed on bonded dies, then vertical height is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The selective silicon thinning process targets only specific regions of the die where excess thickness exists, rather than uniformly thinning the entire die. This localized approach allows for precise control of thickness reduction in critical areas while preserving the original thickness in areas where it is needed for structural integrity or subsequent processing, thereby reducing overall vertical height without excessively increasing precision requirements across the entire die.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases memory capacity, improves stress relief, form factor, and thermal dissipation, allowing for additional device layers within the same physical constraints.
Implementation Method 1
bonding a plurality of first dies to a substrate via a hybrid bonding process
Implementation Method 2
performing a selective silicon (Si) thinning process to reduce a thickness of the plurality of first dies
Implementation Method 3
passivating the plurality of thinned first dies to form a plurality of passivated thinned first dies to protect the plurality of thinned first dies
Implementation Method 4
filling gaps between adjacent dies of the plurality of thinned first dies with a first fill material
Implementation Method 5
forming a plurality of first conductive vias through the first layer to the substrate
Data Source
AI summary
Embodiments of methods of die stacking are provided herein. In some embodiments, a method of die stacking with die-to-wafer bonding includes: bonding a plurality of first dies to a substrate via a hybrid bonding process; performing a selective silicon (Si) thinning process to reduce a thickness of the plurality of first dies that are bonded to form a plurality of thinned first dies; passivating the plurality of thinned first dies to form a plurality of passivated thinned first dies to protect the plurality of thinned first dies; filling gaps between adjacent dies of the plurality of thinned first dies with a first fill material, wherein the plurality of passivated thinned first dies and the first fill material together form a first layer; and forming a plurality of first conductive vias through the first layer to the substrate.