Semiconductor Die Stacking With Small-Pitch Vias for Higher I/O
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Solution Overview
Problem
The manufacturing of miniaturized semiconductor devices faces challenges such as poor electrical interconnection, delamination of components, and high yield loss due to the complexity of manufacturing operations, leading to increased costs and undesirable large form factors, large pitch between vias, and small I/O counts.
Innovation Solution
A semiconductor structure is developed with a substrate, multiple dies, and a molding that includes vias configured in a small pitch, an interconnect structure, and conductive bumps to enhance electrical performance and reduce the overall dimension, allowing for increased I/O terminals and improved electrical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If miniaturized scale semiconductor devices are manufactured, then functionality and integrated circuitry increase, but manufacturing complexity increases causing poor electrical interconnection and delamination
Solution Approach 1:
The patent divides the semiconductor structure into multiple discrete components including separate first and second dies, a substrate, and a molding layer. This segmentation allows each component to be optimized and manufactured independently, then assembled together, reducing overall manufacturing complexity while maintaining high functionality.
Solution Approach 2:
The patent transitions from planar interconnection to three-dimensional vertical interconnection by forming vias through the molding layer to connect the first die to the substrate. This dimensional change enables electrical connectivity without requiring complex lateral routing on the same plane, simplifying the manufacturing process.
2Productivity
If miniaturized scale semiconductor devices are manufactured, then chip integration increases, but electrical interconnection quality deteriorates
Solution Approach 1:
The patent introduces a substrate as an intermediary component between the first die and second die. The substrate provides a stable mechanical and electrical platform that facilitates reliable interconnection between multiple chips, improving electrical interconnection quality while enabling higher chip integration.
Solution Approach 2:
The patent replaces traditional mechanical wire bonding with direct electrical contact through vias and contact pads. This substitution eliminates the mechanical complexity and reliability issues associated with wire bonding, enabling more reliable electrical interconnection in miniaturized devices.
3Ease of manufacture
If traditional semiconductor structure is used, then manufacturing is simpler, but form factor and pitch between vias are large
Solution Approach 1:
The patent changes the pitch parameter by forming vias at closely spaced locations across the molding layer, achieving small pitch between vias. This parameter change enables compact form factor while the modular structure maintains manufacturing simplicity through standardized processes.
Solution Approach 2:
The patent implements a nested structure where the first die and second die are positioned on the substrate, with vias extending through the molding layer to connect underlying structures. This nesting arrangement maximizes space utilization, reducing the overall form factor while maintaining manufacturing feasibility.
4Adaptability or versatility
If manufacturing operations are increased for greater functionality, then device capability improves, but yield loss increases due to manufacturing complexity
Solution Approach 1:
The patent performs preliminary actions by pre-forming contact pads on the substrate and preparing the first die with appropriate contact structures before final assembly. This preliminary preparation ensures proper alignment and connection during subsequent manufacturing steps, reducing defects and yield loss while enabling greater device capability.
Data Source
AI summary
A method of manufacturing a semiconductor structure includes following operations. A substrate is provided. A first die is disposed over the substrate. A second die is provided. The second die includes a via extended within the second die. The second die is disposed over the substrate. A molding is formed around the first die and second die. An interconnect structure is formed. The interconnect structure includes a dielectric layer and a conductive member. The dielectric layer is disposed over the molding, the first die and the second die. The conductive member is surrounded by the dielectric layer. The via is formed by removing a portion of the second die to form a recess extended within the second die and disposing a conductive material into the recess.