Die Stacking Structure With Through-Vias for Dense Fan-Out Packaging
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving high integration density and efficient packaging of semiconductor dies, particularly in shrinking electronic devices, where existing packaging techniques like Package-on-Package (PoP) technology struggle with reduced component density and increased complexity.
Innovation Solution
A die stacking structure is developed, where a first device die is bonded to a second device die with through-vias, and redistribution lines are formed using a fan-out process, eliminating solder regions between them, and encapsulating the first die with an encapsulant that contacts probe pads for reduced probing costs and increased signal paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional Package-on-Package (PoP) technology is used to stack semiconductor packages, then integration density is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The invention divides the semiconductor structure into separate functional components: a first semiconductor die with circuitry and a second semiconductor die with through-vias, which are separately fabricated and then bonded together. This segmentation allows each die to be optimized independently for its specific function, reducing overall packaging complexity while maintaining high integration density.
Solution Approach 2:
The invention transitions from planar packaging to three-dimensional stacking by bonding the first semiconductor die to the second semiconductor die in a vertical arrangement. This dimensional change enables higher integration density within a smaller footprint while the through-vias provide direct vertical interconnections, simplifying the interconnect architecture compared to traditional multi-layer PoP structures.
2Adaptability or versatility
If through-vias are used to connect semiconductor dies, then signal paths are increased, but manufacturing precision requirements increase
Solution Approach 1:
The through-vias are pre-formed in the second semiconductor die during its fabrication process, before bonding to the first die. This preliminary action ensures that the via holes are precisely positioned and etched with controlled dimensions, reducing the precision requirements during the subsequent bonding process. The pre-formed vias can then be directly connected to pad structures without requiring complex real-time alignment.
3Ease of manufacture
If solder regions are eliminated between dies, then manufacturing cost is reduced, but bonding reliability may be affected
Solution Approach 1:
The invention removes the solder intermediate layer from the bonding interface between the first and second semiconductor dies. By directly bonding the pad structure of the first die to the through-via structure of the second die, the complex soldering process is eliminated, reducing manufacturing steps and costs. The direct bond creates a more reliable electrical and mechanical connection without the potential failure modes associated with solder joints.
Data Source
AI summary
A method includes bonding a first device die to a second device die, encapsulating the first device die in a first encapsulant, performing a backside grinding process on the second device die to reveal through-vias in the second device die, and forming first electrical connectors on the second device die to form a package. The package includes the first device die and the second device die. The method further includes encapsulating the first package in a second encapsulant, and forming an interconnect structure overlapping the first package and the second encapsulant. The interconnect structure comprises second electrical connectors.