Die Stacking Structure With Direct Via Interconnects
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving high integration density and efficient packaging of semiconductor dies, particularly in shrinking electronic devices, where existing Package-on-Package (PoP) technologies are limited by the need for smaller and more creative packaging techniques.
Innovation Solution
A die stacking structure is developed, where a first device die is bonded to a second device die with through-vias, and redistribution lines are formed using a fan-out process, eliminating solder regions between them, and encapsulated with probe pads in contact with an encapsulant, allowing for direct contact between redistribution lines and the die stack, enabling efficient interconnects and reduced probing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional Package-on-Package (PoP) technology is used to stack semiconductor packages, then integration density is improved, but device complexity and manufacturing complexity increase due to the need for solder regions and multiple packaging layers
Solution Approach 1:
The patent extracts and eliminates the solder region from the interconnect structure between stacked dies. By forming direct copper-to-copper bonds through aligned vias without intervening solder layers, the design removes unnecessary materials and simplifies the packaging structure while maintaining high integration density through the stacked configuration
Solution Approach 2:
The patent transitions from planar interconnection to three-dimensional vertical stacking. By stacking multiple dies vertically with direct through-via connections, the design achieves high integration density in the vertical dimension while reducing the horizontal footprint, and simplifies the structure by eliminating lateral solder interconnects
2Reliability
If solder regions are used to connect stacked semiconductor packages, then electrical connections are established, but manufacturing precision requirements increase and production costs increase
Solution Approach 1:
The patent removes the solder region from the interconnect path, eliminating the need for solder deposition, reflow processing, and associated precision requirements. The direct copper bond through aligned vias reduces manufacturing steps and precision requirements while maintaining reliable electrical connections
Solution Approach 2:
The patent uses the via structure itself as both the mechanical alignment feature and the electrical interconnect. The same copper-filled via that provides structural support also serves as the electrical pathway, eliminating the need for separate solder interconnects and reducing overall manufacturing complexity
3Reliability
If probe pads are exposed and require probing for testing, then device functionality can be verified, but manufacturing costs and processing time increase
Solution Approach 1:
The patent merges the encapsulant material with the probe pad structure by having the encapsulant directly contact and enclose the probe pads. This integration eliminates separate probing steps by allowing testing to occur through the encapsulant interface, thereby improving manufacturing efficiency while maintaining testing capability
Solution Approach 2:
The encapsulant material serves dual functions: it provides structural protection and encapsulation while simultaneously serving as the testing interface. The probe pads are accessible through the encapsulant without requiring additional probing operations, allowing the structure to perform its own testing function
Data Source
AI summary
A method includes bonding a first device die to a second device die, encapsulating the first device die in a first encapsulant, performing a backside grinding process on the second device die to reveal through-vias in the second device die, and forming first electrical connectors on the second device die to form a package. The package includes the first device die and the second device die. The method further includes encapsulating the first package in a second encapsulant, and forming an interconnect structure overlapping the first package and the second encapsulant. The interconnect structure comprises second electrical connectors.