Quasi-Monolithic Die Stacking for Monolithic Yield Trade-Offs
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Solution Overview
Problem
Current monolithic ICs face challenges due to trade-offs in manufacturing processes, leading to decreased performance and yield, as all circuits on a planar surface must be optimized equally, resulting in longer delays and potential malfunctions that can render the entire die unusable.
Innovation Solution
The quasi-monolithic die architecture involves active and passive dies connected using high-density interconnects with pitches less than 10 microns, allowing for optimized design and manufacturing of each die for specific functionalities, reducing mechanical stress and improving signal and power integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If all circuits on a planar surface are optimized equally in a monolithic IC, then manufacturing uniformity is maintained, but performance and yield decrease due to longer routing delays and potential malfunctions
Solution Approach 1:
The patent divides the monolithic die into multiple separate dies (first die and second die) that are coupled together. This segmentation allows each die to be optimized independently for its specific function while maintaining manufacturing uniformity within each die, thereby resolving the contradiction between manufacturing precision and circuit performance/yield.
2Reliability
If multiple separate dies are used to optimize specific functionalities, then circuit performance and yield improve, but device complexity increases due to additional interconnect requirements
Solution Approach 1:
The patent merges the first die and second die into a single integrated structure with closely spaced interconnects (pitch less than 10 microns). This merging approach maintains the performance benefits of separate optimized dies while reducing the overall complexity by integrating them into a unified package with minimal spacing.
Solution Approach 2:
The patent transitions from a planar arrangement to a three-dimensional stacked configuration where dies are positioned above and below a substrate. This dimensional change allows for optimized signal routing and reduced interconnect complexity by utilizing vertical space rather than horizontal expansion.
3Manufacturing precision
If high-density interconnects with pitch less than 10 microns are used, then interconnect density and signal integrity improve, but manufacturing complexity and cost increase
Solution Approach 1:
The patent changes the critical parameter of interconnect pitch to less than 10 microns, which significantly improves signal integrity and reduces routing delays. This parameter change is achieved through advanced fabrication techniques that, while precise, are integrated into the overall manufacturing process to manage complexity and cost.
Data Source
AI summary
Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a dielectric layer having one or more conductive traces and a surface; a microelectronic subassembly on the surface of the dielectric layer, the microelectronic subassembly including a first die and a through-dielectric via (TDV) surrounded by a dielectric material, wherein the first die is at the surface of the dielectric layer; a second die and a third die on the first die and electrically coupled to the first die by interconnects having a pitch of less than 10 microns, and wherein the TDV is electrically coupled at a first end to the dielectric layer and at an opposing second end to the second die; and a substrate on and coupled to the second and third dies; and an insulating material on the surface of the dielectric layer and around the microelectronic subassembly.