Die Test Circuit for TSV Defect Screening Before 3D Stacking
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Solution Overview
Problem
Testing integrated circuit chips without a memory cell array is challenging due to the difficulty in generating various patterns of data needed for testing, making it difficult to identify defects in signal lines and through silicon vias before stacking, which can lead to wasteful discarding of entire packages if defects are discovered post-packaging.
Innovation Solution
Incorporating a repair circuit with a selection circuit and a selection signal generation circuit in the integrated circuit chip to generate test signals and toggle data paths, allowing for wafer-level testing of base dies without a cell array, and replacing defective through silicon vias with redundant ones.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wafer-level testing is performed on integrated circuit chips without a cell array, then defects can be identified before packaging, but the difficulty in generating various patterns of data needed for testing prevents effective testing
Solution Approach 1:
The patent applies preliminary action by pre-configuring test circuits and data patterns into the integrated circuit chip before packaging. The test circuit includes a cell array, data input circuit, data output circuit, and pattern generation circuit that are all prepared in advance to enable wafer-level testing without requiring complex external testing equipment.
Solution Approach 2:
The patent uses an intermediary approach by introducing a dedicated test circuit as a mediator between the chip functionality and the testing process. This test circuit includes pattern generation circuits that create test data patterns, data input/output circuits that transfer test data, and a cell array that stores and processes test data, thereby simplifying the overall testing system.
2Object-affected harmful factors
If testing is performed after packaging, then the packaging provides protection, but defective chips cannot be identified and the entire package must be discarded
Solution Approach 1:
The patent performs the testing action before packaging by implementing wafer-level testing capability. The test circuits and data patterns are prepared in advance, allowing defects to be identified on the wafer before the packaging process begins, thereby preventing waste of packaging materials and enabling selective packaging of only functional chips.
3Area of stationary object
If three dimensional packaging is used to achieve miniaturization, then vertical stacking reduces footprint, but through silicon vias may be defective and difficult to test
Solution Approach 1:
The patent uses an intermediary test circuit as a mediator to detect defects in through silicon vias. The test circuit includes data input/output circuits that can write test data through the through silicon vias and read back the data, thereby enabling detection of via defects without requiring complex external testing equipment.
Solution Approach 2:
The patent performs preliminary testing of through silicon vias at the wafer level before packaging. The test circuits are configured to write test patterns through the vias and read back the data to verify via functionality, allowing defective vias to be identified and flagged before the packaging process begins.
Data Source
AI summary
An integrated circuit chip includes a first through electrode and a second through electrode formed through the integrated circuit chip, a transmission circuit suitable for selecting one of signals transmitted through the first and second through electrodes, respectively, and transmitting the selected signal to a data line, in response to a selection signal, and a selection signal generation circuit suitable for generating the selection signal by toggling the selection signal, during a test operation.