Die-to-Die Driver Calibration via Delay Lock Loop
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Solution Overview
Problem
Existing high-speed die-to-die interfaces face challenges in achieving optimal drive strength across process, voltage, and temperature (PVT) variations without the use of dedicated impedance calibration blocks, on-die precision resistors, or on-package resistors, which are costly and inefficient.
Innovation Solution
The solution involves calibrating a delay lock loop of a delay line unit cell based on drive and load conditions of driver unit cells, generating a clock signal, and communicating data over the die-to-die interconnect based on this clock signal, thereby achieving optimal drive strength across PVT variations without the need for additional calibration components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If dedicated impedance calibration blocks, on-die precision resistors, or on-package resistors are used for driver calibration, then drive strength accuracy across PVT variations is improved, but silicon area and package cost increase
Solution Approach 1:
The patent extracts the calibration function from dedicated calibration blocks and resistors, eliminating these separate components. Instead, it uses the existing delay lock loop circuitry to perform calibration functions, thereby reducing silicon area while maintaining drive strength accuracy across PVT variations
Solution Approach 2:
The patent makes the delay lock loop circuit perform multiple functions: both its original timing/clocking function and the additional driver calibration function. By programming the delay lock loop with calibration codes, it can adjust driver output impedance without requiring dedicated calibration hardware, thus reducing area overhead
2Measurement precision
If dedicated impedance calibration blocks, on-die precision resistors, or on-package resistors are used for driver calibration, then drive strength accuracy across PVT variations is improved, but package cost increases
Solution Approach 1:
The patent removes the need for on-package resistors and dedicated calibration blocks by extracting the calibration function into the existing delay lock loop circuitry. This elimination of external calibration components directly reduces package cost while maintaining calibration capability
Solution Approach 2:
The delay lock loop circuit serves itself by performing both its original timing function and the additional calibration function. The same circuit resources are reused for calibration without requiring external assistance from dedicated calibration blocks or precision resistors, thereby reducing manufacturing cost
3Speed
If aggressive slew rates are used to achieve faster data rates, then communication speed is improved, but power supply noise increases
Solution Approach 1:
The patent implements dynamic adjustment of driver output impedance through calibrated delay lock loop programming. This allows the slew rate to be optimized for each specific data rate: faster slew rates for lower data rates and controlled slew rates for higher data rates, thereby minimizing power supply noise while achieving the required communication speed
Solution Approach 2:
The patent changes the output impedance parameter of the driver by programming the delay lock loop with specific calibration codes. This parameter adjustment optimizes the slew rate to match the operating data rate, reducing simultaneous switching output noise and power supply noise while maintaining the required data transmission speed
Data Source
AI summary
A method for driver calibration in die-to-die interfaces can include calibrating a delay lock loop of a delay line unit cell, by at least one processor, based on drive and load conditions of one or more driver unit cells of a physical layer of a die-to-die interconnect. The method can additionally include generating a clock signal, by the at least one processor, based on the delay lock loop. The method can further include communicating data, by the at least one processor, over the die-to-die interconnect based on the clock signal. Various other methods and systems are also disclosed.