Die-to-Die Gap Control for Semiconductor Structure
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Solution Overview
Problem
The semiconductor industry faces challenges in controlling warpage of wafers during thermal processing, which can lead to stress-induced cracks in through substrate vias (TSVs) and delamination of underfill materials due to the coefficient of thermal expansion mismatch between the substrate and dies, particularly in multi-die stacked structures.
Innovation Solution
The implementation of a two and a half dimensional integrated circuit (2.5DIC) structure with controlled die-to-die spacing, where the average gap distance between dies is maintained at 50 micrometers or less, utilizing a passive interposer with through substrate vias and underfill material to manage warpage, and the use of a method that includes forming conductive bumps and redistribution layers to electrically and mechanically couple dies, thereby reducing thermal stress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If multiple dies are stacked on an interposer to increase integration density, then the package footprint is reduced, but wafer warpage increases during thermal processing
Solution Approach 1:
The patent segments the substrate into multiple regions with different die attachment patterns. By creating distinct zones (first region with first dies, second region with second dies) and controlling the spacing between them, the warpage induced by thermal expansion mismatch is distributed and managed across different segments rather than affecting the entire wafer uniformly.
Solution Approach 2:
The patent applies local quality by specifying different gap distances for different regions of the substrate. The first gap distance between adjacent first dies is controlled to be within a first range, while the second gap distance between adjacent second dies is controlled to be within a second range. This localized control of spacing allows optimization of warpage management in specific areas.
2Reliability
If die-to-die spacing is reduced to shorten inter-die electrical lines, then electrical resistance and capacitance are reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent changes the critical parameter from absolute gap distance to ratio-based gap distance. By specifying that the first gap distance and second gap distance each fall within specific ranges (0.1 to 10 times a reference dimension), the design provides flexibility in manufacturing while ensuring electrical performance. This parameter transformation makes the system less sensitive to absolute dimensional variations.
Solution Approach 2:
The patent employs a composite approach by combining multiple die types (first dies and second dies) with different characteristics on the same substrate. This allows the structure to benefit from the electrical performance of closely spaced dies while using the specific properties of different die types to manage thermal and mechanical stresses that would otherwise require even tighter spacing.
3Productivity
If through substrate vias are used to connect stacked dies, then vertical interconnect density is increased, but stress-induced cracking increases during thermal processing
Solution Approach 1:
The patent applies preliminary anti-action by pre-configuring the die arrangement and spacing on the substrate before thermal processing occurs. By controlling the gap distances between dies in different regions to fall within specific ranges, the structure is pre-prepared to resist the warpage forces that would otherwise cause TSV cracking during subsequent thermal cycles. The spacing is designed in advance to compensate for expected thermal expansion.
Solution Approach 2:
The patent provides beforehand cushioning by introducing controlled empty spaces (gaps) between adjacent dies. These gaps act as cushioning zones that can accommodate thermal expansion and warpage without transmitting excessive stress to the TSVs. The gap distances are specifically controlled to provide sufficient cushioning while maintaining electrical performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces wafer warpage, minimizes cracking and delamination, and allows for a larger process window and higher yield, while also potentially reducing electrical resistance and capacitance by shortening inter-die electrical lines.
Implementation Method 1
The coefficient of thermal expansion (CTE) or shrinkage of underfill can cause the wafer to warp during the thermal process
Implementation Method 2
The at least two dies have an average spacing between adjacent ones of the at least two dies, and the average spacing is in a direction parallel to the first surface of the substrate, and the average spacing is 200 micrometers or less
Data Source
AI summary
An embodiment is a structure comprising a substrate, a first die, and a second die. The substrate has a first surface and a second surface opposite the first surface. The substrate has a through substrate via extending from the first surface towards the second surface. The first die is attached to the substrate, and the first die is coupled to the first surface of the substrate. The second die is attached to the substrate, and the second die is coupled to the first surface of the substrate. A first distance is between a first edge of the first die and a first edge of the second die, and the first distance is in a direction parallel to the first surface of the substrate. The first distance is equal to or less than 200 micrometers.