Die-to-die interconnect protocol for stacked semiconductor dies
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Solution Overview
Problem
Interconnecting semiconductor dies of different sizes within a single IC package is challenging due to limited pin alignment, restricting access to shared resources and increasing power consumption, especially when the smaller die needs to access resources with many signals.
Innovation Solution
A die-to-die interconnect interface and protocol using a data bus to transfer control and data words between semiconductor dies, where the control word includes a start address for memory-mapped devices, allowing efficient sharing of resources without requiring direct pin alignment and minimizing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If dies of different sizes are stacked, then pin alignment is limited and fewer pins are available for interconnection, but this configuration is necessary to accommodate different die footprints
Solution Approach 1:
The patent introduces a bridge die as an intermediary component between the first and second dies of different sizes. This bridge die provides additional interconnection pathways, allowing the smaller second die to access resources on the larger first die despite limited direct pin alignment. The bridge die acts as a mediator that expands the effective interconnect capacity beyond what direct pin-to-pin connections would allow.
2Device complexity
If fewer pins are used for interconnection, then device complexity is reduced, but resource access capability is limited
Solution Approach 1:
The patent utilizes the third dimension (vertical stacking) to overcome the limitation of limited pin count. By stacking multiple dies including a bridge die, the system creates additional interconnection dimensions. The bridge die in the intermediate layer provides alternative routing paths, effectively increasing resource access capability without requiring more pins on each individual die interface.
3Speed
If direct pin-to-pin interconnection is used, then data transfer speed is limited by pin availability, but this is the conventional and simplest interconnection method
Solution Approach 1:
The patent segments the interconnection function across multiple dies (first die, bridge die, second die) rather than relying on a single direct connection. This segmentation allows data to be routed through optimized paths in the stack, improving data transfer speed by utilizing the bandwidth of multiple interconnect interfaces distributed across the stacked structure.
Data Source
AI summary
A system and method for a die-to-die interconnect interface and protocol for stacked semiconductor dies. One preferred embodiment comprises an integrated circuit (IC) package comprising a first semiconductor die that includes an interface to a memory-mapped device, a second semiconductor die that does not include an interface to a memory mapped device, and a data bus coupling the first semiconductor die to the second semiconductor die (the data bus used to transfer a control word and a data word). The control word comprises a data word start address that corresponds to a location in the memory-mapped device. The data word is transferred from the second semiconductor die to the first semiconductor die and is stored by the first semiconductor die at the location in the memory-mapped device. Both semiconductor dies are mounted within the IC package.