Die-to-Die Interconnect Test Architecture for 3D ICs
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Solution Overview
Problem
The challenge of testing three-dimensional (3D) stacked integrated circuits (ICs) is hindered by limited test access, thermal, and power constraints, making it difficult to effectively verify the operation of interconnects between stacked ICs.
Innovation Solution
A design for test (DFT) architecture that reuses functional flops to emulate boundary scan behavior, employs a linear feedback shift register (LFSR)/multiple input signature register (MISR) approach for at-speed testing, and supports burn-in and parametric tests without using scan automatic test pattern generation (ATPG) or loopback, incorporating joint test action group (JTAG) and internal JTAG (IJTAG) for efficient testing of die-to-die interconnects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If traditional testing methods are used for 3D stacked ICs, then test access is limited, but testing capability is insufficient
Solution Approach 1:
The patent transitions from traditional 2D testing approaches to 3D testing by utilizing the vertical stacking dimension. Test circuits are distributed across multiple stacked dies, enabling test signals to propagate through the inter-die interconnects in the vertical dimension, thereby achieving comprehensive testing of the 3D IC structure while maintaining ease of access.
Solution Approach 2:
The patent implements nested test circuits where boundary scan cells and test logic are embedded within the functional circuitry of each die. These nested test circuits can be activated to test both intra-die connections and inter-die interconnects, providing layered testing capability that maintains operational functionality while enabling thorough verification.
2Reliability
If more test circuits are added to 3D stacked ICs, then testing capability improves, but device complexity increases
Solution Approach 1:
The patent designs test circuits that serve multiple functions: boundary scan operations, inter-die interconnect testing, and intra-die logic testing. The same test infrastructure and control mechanisms are reused across different test modes and targets, reducing the need for separate dedicated test circuits for each function and thereby limiting complexity growth.
Solution Approach 2:
The patent merges the test infrastructure for 2D boundary scan with the 3D inter-die testing requirements by extending the existing boundary scan cell architecture to include inter-die test capabilities. This consolidation allows a unified test approach that handles both planar and vertical interconnects without requiring entirely separate testing systems.
3Reliability
If conventional testing approaches are applied, then thermal and power constraints are exceeded, but effective testing cannot be achieved
Solution Approach 1:
The patent implements periodic or pulsed test signal sequences rather than continuous high-power test stimuli. Test patterns are applied in controlled bursts with idle periods between them, allowing thermal dissipation and preventing excessive temperature rise while still achieving comprehensive fault coverage through repeated testing cycles.
Solution Approach 2:
The patent applies partial testing strategies where not all test circuits are activated simultaneously, but rather in staged or selective groups based on test priorities and thermal budgets. This partial activation approach enables sufficient testing effectiveness while keeping power consumption and thermal generation within acceptable limits.
Data Source
AI summary
A die-to-die repeater circuit includes a transmit circuit coupled to a die-to-die interconnect, the transmit circuit including at least one flip flop to function as a part of a linear feedback shift register (LFSR) to transmit a value across the die-to-die interconnect for design for test (DFT) to check proper operation of the die-to-die interconnect, and a receive circuit coupled to the die-to-die interconnect, the receive circuit including at least one flip flop to function as part of a multiple input shift register (MISR).