Die-to-Die Interconnects for In-Memory Processing

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Solution Overview

Problem

Current memory systems face challenges in efficiently processing data between integrated circuit dies, particularly in scaling memory and processing-in-memory (PIM) capabilities due to limitations in die area and interconnects.

Innovation Solution

The proposed solution involves an apparatus and method that utilize die-to-die (D2D) interconnects to enable data transfer and processing between multiple dies, including a first device with a compute element and memory media, and a second device with a compute element and memory media, allowing for cooperative compute operations and data processing in memory.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If memory capacity is increased using traditional scaling methods, then storage capability is improved, but die area consumption increases and manufacturing cost rises

Engineering Contradiction:

Improvememory capacityVSAvoiddie area

Core Design Contradiction:

Quantity of substanceVSArea of stationary object

Solution Approach 1:

The patent transitions from two-dimensional planar memory expansion to three-dimensional stacked architecture, where multiple memory dies are vertically stacked and connected via through-silicon vias (TSVs). This vertical stacking enables significant memory capacity increase without proportionally increasing the die footprint, effectively resolving the contradiction between memory capacity and die area.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The memory system is divided into multiple independent dies stacked vertically, with each die containing a portion of the total memory capacity. This segmentation allows the system to achieve high total capacity while maintaining reasonable individual die sizes, and enables parallel access to different memory segments.

Inventive Principle:

Principle #1Segmentation

2Productivity

If processing power is increased by adding more compute elements, then computational capability is improved, but power consumption and heat generation increase

Engineering Contradiction:

Improvecomputational capabilityVSAvoidpower consumption

Core Design Contradiction:

ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent merges memory and compute functions into a unified Processing-in-Memory (PIM) architecture, where compute elements are integrated directly with memory structures. This co-location eliminates the need for separate memory and compute units, reducing overall power consumption by eliminating data movement between separate components while maintaining high computational capability.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent introduces specialized interconnect structures and control logic that mediate between memory and compute elements, enabling efficient in-memory processing. This intermediary layer facilitates direct computation on stored data without requiring full data movement to separate compute units, thereby reducing power consumption.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Speed

If data transfer speed between dies is increased, then system performance is improved, but interconnect complexity and manufacturing difficulty increase

Engineering Contradiction:

Improvedata transfer speedVSAvoidinterconnect complexity

Core Design Contradiction:

SpeedVSDevice complexity

Solution Approach 1:

The patent replaces traditional mechanical/electrical interconnect methods with field-based communication through electromagnetic signals transmitted via TSVs and microstrip lines. This substitution enables higher data transfer speeds by utilizing electromagnetic wave propagation rather than physical contact mechanisms, while the standardized transmission line designs keep complexity manageable.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

4Adaptability or versatility

If more interfaces are added to each die for enhanced connectivity, then system versatility is improved, but die area and manufacturing precision requirements increase

Engineering Contradiction:

Improveconnectivity capabilityVSAvoidinterface alignment precision

Core Design Contradiction:

Adaptability or versatilityVSManufacturing precision

Solution Approach 1:

The patent implements universal interface designs that can handle multiple communication functions (data transfer, control signals, power) through standardized TSV and microstrip line structures. This multi-functionality reduces the need for separate specialized interfaces, thereby maintaining connectivity versatility while reducing the number of precision-critical interface locations.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS20250190391A1Systems, methods, and apparatus for processing in memory using die-to-die interconnects

Publication Date: 2025.06.12 SAMSUNG ELECTRONICS CO LTD

AI summary

An apparatus may include a first device including at least one first die including a first interface, a memory media configured to store first information received using the first interface, and a compute element configured to perform, using the first information, a compute operation, and a second device including at least one second die including a second interface configured to receive second information, and a third interface coupled to the first interface and configured to send the first information, wherein the first information may be based on the second information. The at least one second die may include a second memory media configured to store at least a portion of the second information, and a second compute element configured to perform, using the at least a portion of the second information, a second compute operation.