Die-to-Die Interface Sequential Logic Placement
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Solution Overview
Problem
Conventional die-to-die interfaces in multi-die packages require large clock trees due to distributed sequential logic circuits, leading to increased metal and capacitance, which in turn increases power consumption and necessitates the need for improved die-to-die interfaces.
Innovation Solution
The proposed solution involves placing sequential logic circuits along one side of the die-to-die interface subsystem, with clock trees that are smaller and less capacitive, ensuring uniform physical data paths and clock signal lengths to reduce metal and capacitance while maintaining adequate setup and hold times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If sequential logic circuits are distributed under or near their respective contacts in an array, then connectivity density is enabled, but clock tree size and metal capacitance increase
Solution Approach 1:
The patent segments the sequential logic circuits into two distinct groups: transmit sequential logic circuits placed near transmit contacts and receive sequential logic circuits placed near receive contacts. This segmentation allows each clock tree to serve a localized region rather than distributing clocks across the entire die surface, thereby reducing total metal and capacitance while maintaining high connectivity density through the die-to-die interface.
Solution Approach 2:
The patent transitions from a two-dimensional distributed arrangement (sequential logic circuits scattered across the die surface under contacts) to a more organized spatial arrangement where sequential logic circuits are concentrated in specific regions (transmit side and receive side). This dimensional reorganization reduces the clock distribution area while preserving the functional connectivity required for high-density data transmission.
2Productivity
If sequential logic circuits are distributed over the area of the contact array, then data paths are provided, but clock tree metal traces become longer and power consumption increases
Solution Approach 1:
By segmenting the sequential logic circuits into transmit and receive groups located in different regions, the patent creates two separate clock trees that each cover smaller areas. This reduces the total length of metal traces required for clock distribution, thereby reducing capacitance and power consumption while maintaining full data transmission capability through the die-to-die interface.
Solution Approach 2:
The patent applies local quality by placing sequential logic circuits in specific locations optimized for their function: transmit sequential logic circuits are positioned near transmit contacts to minimize transmit clock tree size, and receive sequential logic circuits are positioned near receive contacts to minimize receive clock tree size. This localized placement reduces overall clock distribution requirements and power consumption.
3Adaptability or versatility
If clock trees distribute clock over large contact array area, then all contacts are served, but metal traces are longer and capacitance increases
Solution Approach 1:
The patent divides the clock distribution system into two separate clock trees: a transmit clock tree serving transmit sequential logic circuits and a receive clock tree serving receive sequential logic circuits. Each clock tree is confined to a smaller regional area rather than spanning the entire die, which reduces metal trace length and capacitance while still providing comprehensive coverage of all necessary contacts through the segmented architecture.
Solution Approach 2:
The patent reorganizes the spatial arrangement of sequential logic circuits from a distributed two-dimensional pattern across the entire die to a more concentrated arrangement in specific regions. This dimensional change reduces the clock distribution area required, thereby reducing metal trace length while maintaining full contact coverage through the reorganized layout.
Data Source
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AI summary
A circuit includes a first die having a first array of exposed data nodes, and a second die having a second array of exposed data nodes, wherein a given data node of the first array corresponds to a respective data node on the second array, further wherein the first array and the second array share a spatial arrangement of the data nodes, wherein the first die has data inputs and sequential logic circuits for each of the data nodes of the first array on a first side of the first array, and wherein the second die has data outputs and sequential logic circuits for each of the data nodes of the second array on a second side of the second array, the first and second sides being different.