Die-to-Die Interposer with GSSG Pattern for HBM Integration
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Solution Overview
Problem
The integration of high-bandwidth memory (HBM) with 3D integrated circuits (ICs) is challenging due to high HBM RC delays associated with high-density, fine metal pitch interconnect layers, which cannot meet both high-speed and high-density interconnect requirements simultaneously.
Innovation Solution
A die-to-die interconnect structure with a modified interposer topology, featuring multiple metal interconnect layers arranged in a ground-signal-signal-ground (G-S-S-G) pattern, including virtual dielectric gaps between signal lines to reduce resistance and capacitance, and stacked ground-VIA chains for effective ground shielding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the interposer interconnect layers are designed with high-density and fine metal pitch to meet routing needs, then routing density is improved, but resistance increases and signal quality deteriorates
Solution Approach 1:
The patent applies different metal pitch specifications to different functional regions of the interposer. High-density fine pitch (e.g., 5um) is used in logic-rich regions requiring extensive routing, while lower-density coarser pitch (e.g., 10um) is used in memory regions where routing density is less critical. This local differentiation allows each region to have optimal signal quality while maintaining overall high routing capacity.
Solution Approach 2:
The patent transitions from a single-plane interconnect approach to a multi-layer three-dimensional interconnect structure. By stacking multiple metal layers (M1-M6) with vertical vias (M1V, M2V, etc.), the design achieves high routing density in the horizontal plane while maintaining signal integrity through controlled impedance in the vertical dimension. The alternating pattern layers and via structures create a 3D routing network that resolves the 2D density-quality tradeoff.
2Reliability
If the interposer size is increased to reduce resistance, then electrical performance is improved, but inter-metal capacitance increases and metal pitch must be larger
Solution Approach 1:
The patent segments the interposer into multiple functional blocks (logic blocks, memory blocks, I/O blocks) that are independently interconnected through the multi-layer metal network. Each block can be optimized with appropriate metal pitch and via density, allowing resistance to be managed locally without requiring a uniformly large interposer. The segmented approach distributes the electrical performance requirements across multiple smaller routing paths.
Solution Approach 2:
The patent implements a nested via structure where smaller diameter vias (e.g., 3um M1V) are positioned within or adjacent to larger via structures (e.g., 6um M2V), creating a hierarchical via system. This nesting allows multiple signal paths to share the same vertical space, reducing the overall interposer footprint while maintaining low resistance through multiple parallel via channels.
3Quantity of substance
If fine metal pitch is used to meet high-density requirements, then routing capacity is improved, but HBM RC delays increase
Solution Approach 1:
The patent applies coarser metal pitch (e.g., 10um) specifically in the HBM interface regions and memory stacking areas, while maintaining fine pitch (e.g., 5um) in logic processing regions. This local quality differentiation reduces RC delays for HBM signals without sacrificing routing capacity in the logic blocks. The via dimensions are also locally optimized with larger via sizes in HBM regions to reduce resistance.
Solution Approach 2:
The patent introduces intermediate buffer regions and transition layers between the fine-pitch logic blocks and coarse-pitch HBM regions. These intermediary structures provide impedance matching and signal conditioning, reducing the impact of RC delays at the interfaces between different pitch regions. The multi-layer via structures act as intermediaries to smoothly transition between different metal pitch domains.
Data Source
AI summary
A die-to-die interconnect structure includes an interconnect network including a plurality of metal interconnect layers. The interconnect network is configured to electrically couple a first die and a second die mounted on a top surface of the die-to-die interconnect structure. A first metal interconnect layer of the plurality of metal interconnect layers includes a plurality of ground lines and a plurality of signal lines distributed across the first metal interconnect layer according to a GSSG pattern. In some examples, adjacent signal lines within the first metal interconnect layer are separated by a dielectric region. In some embodiments, a second metal interconnect layer of the plurality of metal interconnect layers is disposed above the first metal interconnect layer and includes a plurality of configurable signal/ground lines. By way of example, each of the plurality of configurable signal/ground lines is disposed over the dielectric region and within the second metal interconnect layer.