Die-to-Die Interconnection Routing for Flexible Multi-Die Packaging
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Solution Overview
Problem
Current integrated circuit (IC) manufacturing techniques face challenges in efficiently interconnecting multiple dies with high resolution and critical dimension accuracy, particularly in multi-chip modules (MCMs) where die-to-die routing is limited by existing packaging technologies.
Innovation Solution
The implementation of monolithic and external die-to-die interconnection methods, including chip-level die-to-die routing and package-level die-to-die routing, using selection devices like multiplexers and demultiplexers, and through-silicon vias (TSVs), which allow for flexible and redundant routing configurations within the semiconductor substrate and external connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional packaging technologies are used for die-to-die routing, then manufacturing simplicity is maintained, but interconnection flexibility and routing capability are limited
Solution Approach 1:
The patent segments the interconnection system into multiple independent routing layers (first set of routing lines, second set of routing lines) with different orientations. This segmentation allows each layer to be optimized independently for specific routing directions, thereby increasing overall interconnection flexibility without proportionally increasing device complexity.
Solution Approach 2:
The patent transitions from conventional two-dimensional routing to a three-dimensional routing architecture by stacking multiple routing layers vertically. This dimensional change enables complex interconnections between multiple dies by utilizing vertical space, providing enhanced routing capability while maintaining manufacturing feasibility through standardized layering processes.
2Productivity
If monolithic chip-level die-to-die routing is implemented, then interconnection efficiency is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent implements preliminary action by pre-forming via holes and routing lines on each individual die before the dies are interconnected. This allows each die to be manufactured and tested independently with standard precision requirements, and the high-efficiency monolithic routing is established after bonding, thereby achieving interconnection efficiency without imposing excessive precision requirements on the manufacturing process.
Solution Approach 2:
The patent uses an intermediary substrate or carrier to hold multiple dies in their final interconnected arrangement during the routing formation process. This intermediary structure provides mechanical support and alignment references, enabling efficient chip-level routing to be implemented without requiring ultra-precise direct alignment between adjacent dies on the substrate.
3Reliability
If redundant routing layouts are designed, then yield is improved, but device complexity increases
Solution Approach 1:
The patent applies local quality by providing redundant routing paths only in specific critical areas where yield enhancement is most beneficial, rather than duplicating all routing throughout the entire device. The first and second sets of routing lines are strategically placed to provide alternative paths for critical signal connections, improving yield without unnecessarily increasing overall device complexity.
Solution Approach 2:
The patent implements partial redundancy by providing alternative routing paths for only the most critical interconnections that would have the greatest impact on yield if failed. This partial action approach achieves sufficient yield improvement without the excessive complexity that would result from complete redundancy of all routing paths.
Data Source
AI summary
Multi-die structures and methods of fabrication are described. In an embodiment, a multi-die structure includes a first die, a second die, and die-to-die routing connecting the first die to the second die. The die-to-die interconnection may be monolithically integrated as a chip-level die-to-die routing, or external package-level die-to-die routing.