Die-Wise LLR Estimation for Multi-Die Memory LDPC Decoding
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Solution Overview
Problem
LDPC decoders experience significant performance loss due to asymmetry in channels, such as NAND and 3D XPoint memory, where different dies exhibit varying error characteristics, leading to unequal error correction performance.
Innovation Solution
Estimating crossover probabilities and leveraging log-likelihood ratios (LLRs) for improved min-sum decoding, allowing for separate error correction of each die and minimal overhead in terms of area and latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate error correction for each die is implemented, then error correction performance is improved, but device complexity increases
Solution Approach 1:
The patent divides the codeword into multiple sections, each corresponding to a specific die. The LDPC decoder processes each section separately with die-specific parameters, allowing targeted error correction for each die while maintaining overall system reliability.
Solution Approach 2:
The patent applies different error correction parameters and thresholds to different die sections based on their individual error characteristics. Each die section receives customized decoding parameters optimized for its specific error rate and asymmetry, improving overall correction performance.
2Measurement precision
If die-wise RBER estimation is performed, then measurement precision is improved, but loss of time increases
Solution Approach 1:
The patent performs RBER estimation and channel parameter characterization during idle periods or alongside normal read operations. By preparing die-specific error rate data in advance, the actual decoding process can use pre-computed parameters without significant latency penalty.
Solution Approach 2:
The system uses the actual error patterns observed during normal operation to continuously refine and update die-specific RBER estimates. This self-updating mechanism maintains high measurement precision without requiring separate dedicated measurement operations that would increase latency.
Data Source
AI summary
Examples include techniques for improving low-density parity check decoder performance for a binary asymmetric channel in a multi-die scenario. Examples include logic for execution by circuitry to decode an encoded codeword of data received from a memory having a plurality of dies, bits of the encoded codeword stored across the plurality of dies, using predetermined log-likelihood ratios (LLRs) to produce a decoded codeword, return the decoded codeword when the decoded codeword is correct, and repeat the decoding using the predetermined LLRs when the decoded codeword is not correct, up to a first number of times when the decoded codeword is not correct. When a correct decoded codeword is not produced using predetermined LLRs, further logic may be executed to estimate the LLRs for a plurality of buckets of the plurality of dies, normalize magnitudes of the estimated LLRs, decode the encoded codeword using the normalized estimated LLRs to produce a decoded codeword, return the decoded codeword when the decoded codeword is correct, and repeat the decoding using the normalized estimated LLRs when the decoded codeword is not correct, up to a second number of times when the decoded codeword is not correct.