Bumpless Superconducting Vias for Dense 3D Qubit Interconnects
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Solution Overview
Problem
High-density 3D chip integration techniques face challenges in maintaining bump yield and bonding precision due to the need for precise alignment and planarity control, especially as bump diameters shrink, leading to increased stress on bumps and complexity in underfill material formulation and dispensing.
Innovation Solution
A method involving the use of a dielectric layer to align and bond substrates, forming high-aspect-ratio vias through etching, and filling these vias with superconducting material to create electrical connections, eliminating the need for traditional bump bonding and simplifying the underfill process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If bump diameters are shrunk to achieve higher interconnect density, then interconnect density is improved, but manufacturing precision deteriorates due to difficulty in maintaining bump yield and bonding precision
Solution Approach 1:
The patent replaces the mechanical bump bonding system with a via-based electrical connection system. Instead of using raised metallic bumps that require precise mechanical alignment and bonding, the invention uses through-substrate vias filled with conductive material that are aligned and bonded using a dielectric layer, eliminating the need for complex bump formation and bonding processes
Solution Approach 2:
The patent introduces a dielectric layer as an intermediary between substrates to achieve alignment and bonding. This dielectric layer serves as a mediator that enables precise positioning and electrical connection without requiring direct bump-to-bump contact, thereby improving manufacturing precision while maintaining high interconnect density
2Length of moving object
If bump diameters are shrunk to achieve smaller interconnects, then interconnect size is reduced, but device complexity increases due to additional constraints on underfill materials and dispensing processes
Solution Approach 1:
The patent extracts and eliminates the underfill requirement from the bump bonding process. By using a dielectric layer-based alignment and bonding system with through-substrate vias, the invention removes the need for complex underfill materials and dispensing processes that are necessary to support and protect small bumps, thereby reducing device complexity while maintaining small interconnect sizes
3Length of stationary object
If bump heights are decreased due to smaller diameters, then chip-to-chip spacing is reduced, but stress on bumps increases due to limitations in aspect ratio of plated pillars
Solution Approach 1:
The patent replaces the plated pillar bump structure with a through-substrate via structure. This substitution allows for better stress distribution as the conductive material fills the entire via depth, eliminating the aspect ratio limitations of plated pillars and reducing stress concentration while maintaining reduced chip-to-chip spacing
Data Source
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AI summary
Described is a method of forming an integrated circuit (50) that comprises a plurality of conductive contact pads (60) on a surface of a first substrate (52), and a dielectric layer (54) overlying the first substrate and the conductive contact pads, which may be coupled to respective qubits (62). A second substrate (56) overlies the dielectric layer, and a plurality of superconducting contacts (58) extend through the second substrate and the dielectric layer such that each superconducting contact is aligned with and in contact with a respective conductive contact pad and may be coupled to a respective resonator (64).