Dielectric Anchor Void in Nanowire Gates for Easier Gate Isolation
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Solution Overview
Problem
The scaling of features in integrated circuits poses challenges in maintaining performance and control, particularly in achieving high aspect ratio gate plugs and ensuring proper gate end-to-end isolation, which are critical for advanced technology nodes.
Innovation Solution
The implementation of self-aligned anchors and the selective removal of certain anchors in integrated circuit structures, allowing for the formation of cut gates with reduced aspect ratios and enabling seamless work function metal deposition, thereby improving process control and yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional processes are used to fabricate tri-gate transistors on bulk silicon substrates, then manufacturing cost is reduced and fabrication process is simplified, but maintaining mobility improvement and short channel control at dimensions below 10 nanometer node becomes challenging
Solution Approach 1:
The patent transitions from planar 2D transistors to three-dimensional tri-gate and nanowire structures. By adding vertical dimensionality with multiple gates wrapping around the channel, the invention achieves superior short channel control and mobility improvement while maintaining compatibility with bulk silicon substrates, thus resolving the contradiction between ease of manufacture and device performance at scaled dimensions.
Solution Approach 2:
The patent employs composite material structures including silicon-germanium sacrificial layers combined with silicon nanowires, and multi-layer gate stacks with different materials (e.g., tungsten, cobalt, titanium nitride). These composite structures enable precise control of electrical properties while maintaining manufacturability on bulk silicon, addressing both the ease of manufacture and reliability concerns.
2Productivity
If feature dimensions are reduced to increase device density, then capacity is increased, but the constraints on lithographic processes become overwhelming and trade-off between critical dimension and spacing increases
Solution Approach 1:
By moving from two-dimensional planar transistors to three-dimensional structures (tri-gate and nanowires), the patent achieves higher device density without proportionally reducing lateral feature dimensions. This vertical stacking approach increases capacity while avoiding the lithographic precision constraints that would otherwise be required for further lateral scaling.
Solution Approach 2:
The patent segments the channel into multiple nanowires stacked vertically, with each nanowire providing an independent conduction path. This segmentation allows increased device density through vertical stacking while maintaining larger lateral dimensions that are easier to pattern with conventional lithography, thus resolving the contradiction between productivity and manufacturing precision.
3Reliability
If gate plugs are formed with high aspect ratios to achieve proper gate end-to-end isolation, then isolation is improved, but process control becomes more difficult and yield decreases
Solution Approach 1:
The patent introduces dielectric anchor structures as intermediary elements during the gate plug formation process. These anchors provide mechanical support and process control references, enabling the formation of high aspect ratio gate plugs with improved process control and yield while maintaining the necessary gate end-to-end isolation.
Solution Approach 2:
The patent performs preliminary formation of dielectric anchors and sacrificial material structures before forming the final gate plugs. This preliminary action creates a structured framework that guides subsequent etching and deposition processes, making it easier to achieve proper gate end-to-end isolation while maintaining process control, thus resolving the contradiction between reliability and manufacturing precision.
Data Source
AI summary
Integrated circuit structures having a dielectric anchor void, and methods of fabricating integrated circuit structures having a dielectric anchor void, are described. For example, an integrated circuit structure includes a sub-fin in a shallow trench isolation (STI) structure. A plurality of horizontally stacked nanowires is over the sub-fin. A gate dielectric material layer is surrounding the horizontally stacked nanowires. A gate electrode structure is over the gate dielectric material layer. A dielectric anchor is laterally spaced apart from the plurality of horizontally stacked nanowires and recessed into a first portion of the STI structure. A second portion of the STI structure on a side of the plurality of horizontally stacked nanowires opposite the dielectric anchor has a trench therein. A dielectric gate plug is on the dielectric anchor.