Dielectric Anchor Void Structure for Nanowire Gate Plug Scaling
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Solution Overview
Problem
The challenge of scaling multi-gate and nanowire transistors is exacerbated by the constraints on lithographic processes, leading to difficulties in patterning features with critical dimensions and spacing, particularly in the fabrication of tri-gate transistors on bulk silicon substrates, which affects mobility and short channel control.
Innovation Solution
The implementation of self-aligned dielectric anchor voids and selective removal of anchors in integrated circuit structures, allowing for reduced aspect ratio gate plugs and improved process control through techniques like plug-last approaches, which facilitate seamless work function metal deposition and reduce void formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithographic processes are used to pattern features, then manufacturing process is simpler, but critical dimension control and spacing between features deteriorate
Solution Approach 1:
The patent segments the patterning process into multiple steps using self-aligned spacer formation. First, mandrels are patterned, then spacers are formed on the mandrels through conformal deposition and anisotropic etching. This multi-stage segmentation allows achieving sub-lithographic critical dimensions while maintaining process control through self-alignment mechanisms.
Solution Approach 2:
The patent employs preliminary actions by forming sacrificial mandrels and spacers before final feature definition. The mandrels are formed first, then spacers are deposited and etched to define the actual feature locations. This preliminary structuring enables precise critical dimension control and spacing without requiring direct lithographic patterning at the final scale.
2Area of moving object
If feature size is reduced to increase density, then capacity increases, but lithographic constraints and manufacturing difficulty worsen
Solution Approach 1:
The patent transitions from two-dimensional lithographic patterning to three-dimensional self-aligned spacer formation. By depositing conformal layers and performing anisotropic etching, the critical dimensions are defined by film thickness and etch selectivity rather than lithographic resolution, effectively moving the manufacturing challenge to the deposition and etching domains where better control is achievable.
Solution Approach 2:
The patent introduces sacrificial mandrels as intermediary structures that facilitate the formation of final features. These mandrels serve as temporary templates that enable precise feature placement and dimension control through self-aligned spacer formation, eliminating the need for direct lithographic patterning at the target critical dimension.
3Ease of manufacture
If tri-gate transistors are fabricated on bulk silicon substrates, then cost is reduced and fabrication is simpler, but mobility improvement and short channel control deteriorate
Solution Approach 1:
The patent applies local quality by forming raised source and drain regions with specific doping profiles in the bulk silicon substrate. These localized modifications provide the necessary short channel control and mobility enhancement only where required, while maintaining the overall simplicity and cost advantages of bulk silicon fabrication. The self-aligned spacer structures also provide localized geometric control for improved channel confinement.
Data Source
AI summary
Integrated circuit structures having a dielectric anchor void, and methods of fabricating integrated circuit structures having a dielectric anchor void, are described. For example, an integrated circuit structure includes a sub-fin in a shallow trench isolation (STI) structure. A plurality of horizontally stacked nanowires is over the sub-fin. A gate dielectric material layer is surrounding the horizontally stacked nanowires. A gate electrode structure is over the gate dielectric material layer. A dielectric anchor is laterally spaced apart from the plurality of horizontally stacked nanowires and recessed into a first portion of the STI structure. A second portion of the STI structure on a side of the plurality of horizontally stacked nanowires opposite the dielectric anchor has a trench therein. A dielectric gate plug is on the dielectric anchor.