Dielectric Bonding Structure for Void-Free DRAM Bit Lines

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Solution Overview

Problem

The challenge in DRAM manufacturing is the formation of voids at the interface between metal layers during substrate bonding, leading to unstable bit lines and low yield, which is exacerbated by shrinking word line spacing.

Innovation Solution

Utilizing a fusion bonding technique between dielectric layers on substrates to form a bonding structure, eliminating voids at the interface and stabilizing bit lines, thereby enhancing yield.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Strength

If metal to metal bonding is used during substrate bonding, then bonding strength is achieved, but voids are formed at the interface between metal layers causing bit line instability

Engineering Contradiction:
Improvebonding strengthVSAvoidbit line stability
Core Design Contradiction:
StrengthVSReliability

Solution Approach 1:

A dielectric layer is introduced as an intermediary material between the metal layers during substrate bonding. This dielectric layer prevents direct metal-to-metal contact that causes void formation, while still enabling effective bonding. The dielectric material fills the interface region and eliminates voids at the bonding interface, ensuring bit line stability without compromising bonding strength.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The bonding process parameters are changed from traditional metal-to-metal bonding to bonding with dielectric material involvement. This includes modifying the bonding sequence where dielectric layers are bonded first or simultaneously with metal layers, changing the physical and chemical state of the bonding interface to prevent void formation while maintaining bonding integrity.

Inventive Principle:
Principle #35Parameter changes

2Area of moving object

If word line spacing is shrunk to increase device density, then device integration is improved, but void formation at metal interface is exacerbated

Engineering Contradiction:
Improvedevice densityVSAvoidvoid formation control
Core Design Contradiction:
Area of moving objectVSManufacturing precision

Solution Approach 1:

The dielectric layer serves as a mediator that becomes increasingly important as word line spacing shrinks. In high-density devices with reduced spacing, the dielectric material provides a stable, void-free interface that maintains manufacturing precision even when feature sizes are reduced, preventing the exacerbation of void formation that would otherwise occur with tighter spacing.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If fusion bonding technique is used between dielectric layers, then voids are eliminated at interface, but process complexity increases

Engineering Contradiction:
Improvebit line stabilityVSAvoidbonding process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The fusion bonding technique utilizes parameter changes in the dielectric material properties (such as temperature, pressure, or chemical state) to achieve void-free bonding. By controlling these parameters during the bonding process, the dielectric layers fuse together seamlessly, eliminating voids at the interface without requiring excessively complex process equipment or multiple sequential steps.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution results in bit lines free of voids, improving the performance and yield of semiconductor devices by preventing bit line collapse.

Implementation Method 1

a fusion bonding technique is utilized. Fusion bonding technique involves bonding two dielectric layers formed on two individual substrates

Methodology Applied
Scientific EffectFusion bonding: Welding

Data Source

PatentUS12457733B2Semiconductor device having bonding structure and method of manufacturing the same
Publication Date: 2025.10.28 NAN YA TECH
  • US12457733B2 patent drawing
  • US12457733B2 patent drawing
  • US12457733B2 patent drawing

AI summary

A semiconductor device and method for manufacturing the same are provided. The semiconductor device includes a substrate, a bonding structure, a bit line, and a word line. The bonding structure is disposed on the substrate. The bit line is disposed on the bonding structure. The channel layer is disposed on the bit line. The word line surrounds the channel layer. The bonding structure includes a dielectric material.