3D IC Dielectric Bonding via Post-Bond TSV Formation

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Solution Overview

Problem

Current 3D wafer stacking technologies face challenges with adhesive bonding, which limits in-fab processing and raises reliability concerns due to thermal instability and alignment issues with pre-formed through silicon vias (TSV)s across wafer diameters.

Innovation Solution

The method involves forming TSVs post-bonding, using oxide-to-oxide bonding (insulator-to-insulator bonding) without pre-formed vias, eliminating alignment issues and relying on insulating materials for bonding interfaces, allowing for subsequent via formation and conductive filling to establish electrical connections.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If adhesive bonding is used for 3D wafer stacking, then bonding can be achieved, but thermal instability and alignment issues with pre-formed TSVs occur

Engineering Contradiction:

Improvebonding reliabilityVSAvoidthermal stability

Core Design Contradiction:

ReliabilityVSStability of the object's composition

Solution Approach 1:

The patent removes pre-formed TSVs from the bonding interface preparation process. Instead of forming TSVs before bonding (which causes alignment issues), the method forms TSVs after bonding is complete, extracting the TSV formation step from the pre-bonding preparation and eliminating the associated alignment problems between wafers

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent inverts the conventional sequence of operations by performing TSV formation after bonding rather than before. This reversal of the process sequence (bonding first, then via formation) eliminates the alignment challenges that arise when trying to match pre-formed vias across wafer surfaces during bonding

Inventive Principle:

Principle #13The other way round (Inversion)

2Reliability

If pre-formed through silicon vias are used before bonding, then electrical connections can be established, but alignment issues across wafer diameters occur

Engineering Contradiction:

Improveelectrical connection reliabilityVSAvoidvia alignment precision

Core Design Contradiction:

ReliabilityVSManufacturing precision

Solution Approach 1:

The patent performs preliminary bonding of the wafers together first, establishing a stable mechanical and electrical foundation. Only after this preliminary bonding is complete are the TSVs formed, allowing the bonding interface to be established without the complexity of coordinating via alignment during the bonding process itself

Inventive Principle:

Principle #10Preliminary action

3Ease of manufacture

If adhesive materials are used for bonding, then bonding can be achieved, but in-fab processing is limited and reliability concerns arise

Engineering Contradiction:

Improvebonding processabilityVSAvoidbonding reliability

Core Design Contradiction:

Ease of manufactureVSReliability

Solution Approach 1:

The patent replaces adhesive-based chemical bonding with a mechanical/electrical bonding approach using direct wafer bonding techniques. By eliminating the need for adhesive materials and forming bonds through direct contact and subsequent TSV formation, the method enables standard in-fab processing while improving reliability by removing the thermal instability associated with polymeric adhesives

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances reliability and processing flexibility by avoiding alignment challenges and thermal issues associated with adhesives, enabling robust electrical communication between integrated circuit devices in 3D stacked structures.

Implementation Method 1

forming a 3D, bonded IC device by aligning and bonding the first insulating layer of the first IC device to the second insulating layer of the second IC device

Methodology Applied

Scientific EffectOxide-to-oxide bonding: Diffusion Welding

Data Source

PatentUS9406561B2Three dimensional integrated circuit integration using dielectric bonding first and through via formation last

Publication Date: 2016.08.02 INTERNATIONAL BUSINESS MACHINE CORPORATION

AI summary

A method of implementing three-dimensional (3D) integration of multiple integrated circuit (IC) devices includes forming a first insulating layer over a first IC device; forming a second insulating layer over a second IC device; forming a 3D, bonded IC device by aligning and bonding the first insulating layer to the second insulating layer so as to define a bonding interface therebetween, defining a first set of vias within the 3D bonded IC device, the first set of vias landing on conductive pads located within the first IC device, and defining a second set of vias within the 3D bonded IC device, the second set of vias landing on conductive pads located within the second device, such that the second set of vias passes through the bonding interface; and filling the first and second sets of vias with a conductive material.