3D Semiconductor Package Direct Dielectric Bonding
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Solution Overview
Problem
The semiconductor industry faces challenges in miniaturization and integration density, requiring innovative packaging techniques to achieve smaller form factors, higher performance, and lower power consumption, while existing bonding methods are limited by the need for solder joints and underfill processes, which increase manufacturing defects and costs.
Innovation Solution
The method involves direct bonding of functional chips using fusion and hybrid bonding techniques, eliminating the need for solder bumps and underfill, and integrating multiple chips in a single package with Chip-to-Wafer level packaging, which reduces manufacturing errors and costs, and provides a system-in-package (SiP) solution with increased input/output density and low via aspect ratio.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional bonding techniques (solder joints and underfill) are used to bond semiconductor wafers, then reliable electrical connection and mechanical support are achieved, but manufacturing complexity and cost increase, and defect rates rise
Solution Approach 1:
The patent removes solder joints and underfill materials from the bonding process, achieving direct wafer-to-wafer bonding. This extraction of unnecessary components simplifies the manufacturing process while maintaining electrical connection reliability through direct bonding interfaces.
Solution Approach 2:
The patent introduces a bonding interface layer that facilitates direct bonding between wafers without requiring solder joints or underfill. This intermediary bonding mechanism enables reliable electrical connection while eliminating the complexity of traditional multi-layer bonding processes.
2Quantity of substance
If minimum feature size is continuously reduced to increase integration density, then more components can be integrated into a given area, but manufacturing precision requirements and defect sensitivity increase
Solution Approach 1:
The patent transitions from planar 2D integration to 3D stacked integration, allowing more components to be integrated by utilizing the vertical dimension. This approach increases integration density without continuously shrinking feature sizes, thereby reducing the stringent precision requirements associated with sub-20nm manufacturing.
Solution Approach 2:
The patent implements stacked semiconductor wafers where multiple active circuits are fabricated on different wafers that are bonded together in a vertical stack. This nesting approach allows higher integration density while maintaining larger, more manufacturable feature sizes on each individual wafer.
3Volume of moving object
If stacked semiconductor devices are used to reduce form factor, then smaller package size and higher density are achieved, but bonding process complexity and defect risk increase
Solution Approach 1:
The patent eliminates solder joints and underfill materials from the stacked device bonding process, significantly simplifying manufacturing while achieving reliable wafer-to-wafer bonds. This extraction reduces the number of process steps and materials required, making stacked device fabrication more manageable despite the increased complexity of multi-wafer stacking.
4Ease of manufacture
If direct bonding of functional chips is implemented to eliminate solder joints and underfill, then manufacturing defects and costs are reduced, but achieving reliable electrical connection becomes more challenging
Solution Approach 1:
The patent introduces a specialized bonding interface layer that mediates between the chip surfaces, enabling direct bonding while ensuring reliable electrical connection. This intermediary layer facilitates charge carrier transport across the bond interface without requiring solder joints or underfill materials, thus maintaining manufacturing simplicity while guaranteeing connection reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of smaller form factor semiconductor packages with increased input/output density, reduced manufacturing defects, and lower costs by eliminating the need for solder joints and underfill, while enhancing signal transmission performance and flexibility in chip stacking.
Implementation Method 1
bonding a second die to the first die includes fusion bonding a dielectric layer of the second die to a bonding layer
Data Source
AI summary
An embodiment method for forming a semiconductor package includes attaching a first die to a first carrier, depositing a first isolation material around the first die, and after depositing the first isolation material, bonding a second die to the first die. Bonding the second die to the first die includes forming a dielectric-to-dielectric bond. The method further includes removing the first carrier and forming fan-out redistribution layers (RDLs) on an opposing side of the first die as the second die. The fan-out RDLs are electrically connected to the first die and the second die.