Differentiated Dielectric Boundary Walls for Nanowire Strain Control
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Solution Overview
Problem
The challenge in semiconductor manufacturing lies in maintaining mobility improvement and short channel control as device dimensions scale below the 10 nanometer node, particularly in multi-gate and nanowire transistors, where lithographic processes face constraints due to the trade-off between feature size and spacing, and conventional boundary wall materials do not optimize strain for both NMOS and PMOS transistors.
Innovation Solution
Implementing differentiated dielectric boundary walls with silicon nitride for N-N and N-P boundary walls and tungsten oxide or titanium oxide for P-P boundary walls to provide orthogonal compressive and tensile stress, respectively, along with a 'plug-last' approach for gate dielectric layer deposition to reduce gate cut depth and enhance strain compatibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional boundary wall materials are used, then manufacturing process is simplified, but strain optimization for both NMOS and PMOS transistors cannot be achieved
Solution Approach 1:
The patent applies local quality by using different dielectric materials (silicon nitride for N-N and N-P boundaries, tungsten oxide or titanium oxide for P-P boundaries) at different locations to provide locally optimized strain conditions for NMOS and PMOS transistors respectively
Solution Approach 2:
The patent employs composite materials by combining multiple dielectric materials with different mechanical properties (silicon nitride providing compressive strain, tungsten oxide/titanium oxide providing tensile strain) to simultaneously satisfy the strain requirements of both NMOS and PMOS devices
2Manufacturing precision
If gate dielectric layer is deposited before gate cut, then gate dielectric coverage is complete, but gate cut depth increases and metal fill creates voids
Solution Approach 1:
The patent applies preliminary action by depositing the gate dielectric layer after the gate cut is made, ensuring that the dielectric is deposited only in regions where it is ultimately needed, avoiding the need for deep gate cuts through metal regions and preventing void formation during subsequent metal fill operations
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves transistor performance by optimizing strain for both NMOS and PMOS transistors, reduces void formation during metal fill, and enables seamless work function metal deposition, enhancing the overall efficiency of integrated circuit structures.
Implementation Method 1
silicon nitride for N-N and N-P boundary walls to provide orthogonal compressive stress
Implementation Method 2
tungsten oxide or titanium oxide for P-P boundary walls to provide orthogonal compressive and tensile stress
Data Source
AI summary
Integrated circuit structures having differentiated dielectric boundary walls, and methods of fabricating integrated circuit structures having differentiated dielectric boundary walls, are described. For example, an integrated circuit structure includes a sub-fin in a trench isolation structure. A plurality of horizontally stacked nanowires is over the sub-fin. A gate dielectric material layer is surrounding the horizontally stacked nanowires. A gate electrode structure is over the gate dielectric material layer. A dielectric boundary wall is laterally spaced apart from the plurality of horizontally stacked nanowires and recessed into a portion of the trench isolation structure. The dielectric boundary wall has a composition including a metal and oxygen. A dielectric gate plug is on the dielectric boundary wall.