Compliant Dielectric Bumps for Wafer Terminal Height Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor chip packaging methods face challenges such as warpage due to differential thermal expansion and uneven terminal heights, which complicate processing and testing, and can lead to solder mask issues causing terminal recess and strip fracture.
Innovation Solution
A method involving a mold with depressions to form precise, uniform dielectric bumps on a wafer surface, followed by the formation of conductive terminals and a solder mask with aligned apertures, allowing for precise terminal positioning and deformation during testing and mounting, while the conductive posts project above the solder mask for reliable engagement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a continuous compliant layer is formed on the wafer surface, then terminal movability is improved, but warpage increases due to differential thermal expansion
Solution Approach 1:
The continuous compliant layer is segmented into discrete compliant bumps distributed across the wafer surface. Each bump is approximately 5-10 micrometers in height and spaced 10-50 micrometers apart. This segmentation provides localized compliance at terminal locations while minimizing overall wafer warpage, as the discrete bumps do not create the same differential thermal expansion stresses as a continuous layer would.
Solution Approach 2:
Compliance is provided locally at specific bump locations rather than uniformly across the entire wafer surface. The compliant bumps are positioned to coincide with terminal locations, providing movability where needed while leaving the rest of the wafer structure rigid and stable during processing.
2Ease of operation
If terminal heights are made uneven to facilitate engagement, then ease of operation is improved, but manufacturing precision deteriorates
Solution Approach 1:
The compliant bumps are formed in advance with uniform heights through a molding process that ensures precise dimensional control. This preliminary formation of uniformly sized compliant elements allows subsequent terminal formation on top of the bumps to achieve both height uniformity and engagement capability, as the compliance is built into the foundation structure rather than requiring variable terminal heights.
3Object-generated harmful factors
If solder mask extends to the terminal surface, then solder spread is controlled, but terminal engagement is hindered due to recess
Solution Approach 1:
The solder mask is applied selectively to cover only the compliant bump surfaces while leaving the terminal surfaces exposed. This localized masking approach controls solder spread on the bumps during mounting while maintaining full terminal engagement capability, as the terminals remain accessible on the upper surface without being recessed by the solder mask material.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces warpage, ensures all terminals can be engaged simultaneously, and minimizes solder spread and strip fracture, providing reliable testing and mounting with reduced stress on bonding materials.
Implementation Method 1
a mold having a working surface incorporating a plurality of depressions is formed. The mold is placed over a front surface of a wafer element so that the depressions of the mold align with chip regions of the wafer element. A dielectric material is deposited over the working surface of the mold so that the dielectric material fills the depressions of the mold.
Implementation Method 2
The dielectric material is cured to form a set of bumps, each bump having a precisely controlled height above the front surface of the wafer element.
Data Source
AI summary
A dielectric structure is formed by a molding process, so that a first surface of a dielectric structure is shaped by contact with the mold. The opposite second surface of the dielectric structure is applied onto the front surface of a wafer element. The dielectric layer may include protruding bumps and terminals may be formed on the bumps. The bumps may be of a precise height. The terminals lie at a precisely controlled height above the front surface of the wafer element. The terminals may include projecting posts which extend above a surrounding solder mask layer to facilitate engagement with a test fixture. The posts are immersed within solder joints when the structure is bonded to a circuit panel.