Dielectric Cap Layer for Reduced Defectivity in Replacement Gate Contacts
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Solution Overview
Problem
The continuous shrinkage of transistor elements in integrated circuits leads to challenges in forming reliable contact elements with high-k metal gate electrode structures, resulting in significant defectivity and device failures due to issues like metal agglomeration, cracks, and increased contact resistivity during the chemical mechanical polishing process.
Innovation Solution
A dielectric cap layer is formed above the gate electrode structure to mask the metal gate electrodes, reducing the aspect ratio of contact openings and filling cracks, while using established polishing processes to remove excess material, thereby minimizing defects and leakage paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the dimensions of circuit elements are reduced to increase packing density, then the overall complexity of the manufacturing process increases, but device performance improves
Solution Approach 1:
The gate electrode structure is segmented into multiple functional layers: a high-k dielectric material layer (first conductive material) and a metal cap layer (second conductive material). This segmentation allows each layer to perform its specific function optimally while simplifying the overall manufacturing process by using standard deposition and planarization techniques on each layer independently.
Solution Approach 2:
The gate electrode uses a composite structure combining high-k dielectric material with metal cap layer. This composite approach enables the structure to simultaneously achieve high capacitance (from high-k material) and low resistance (from metal layer), reducing the need for complex multi-material processing while improving device performance.
2Reliability
If copper is used in metallization systems to improve electrical performance, then electromigration behavior improves, but copper diffusion into transistor elements alters transistor characteristics
Solution Approach 1:
The conductive gate electrode is segmented into two distinct material layers: a high-k dielectric material layer and a metal cap layer. This segmentation allows copper to be confined to the metal cap layer where it provides superior electrical performance, while the high-k dielectric layer acts as a barrier preventing copper diffusion into the transistor channel, thus resolving the contradiction between electrical performance and diffusion control.
3Shape
If chemical mechanical polishing is used to remove excess contact material, then planarity is improved, but metal agglomeration and cracks increase defectivity
Solution Approach 1:
A capping layer is formed over the gate electrode structure before contact hole formation and filling. This preliminary action protects the underlying metal layers during subsequent CMP processing, preventing metal agglomeration and crack formation while still allowing excess contact material to be removed and planarity to be achieved.
Solution Approach 2:
The capping layer serves as a protective cushion that absorbs the mechanical and chemical stresses of the CMP process. By placing this protective layer beforehand, the vulnerable metal gate electrode structures are shielded from the harsh polishing conditions that would otherwise cause metal agglomeration and cracking, thus maintaining contact element integrity while achieving planarity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the defect rate and maintains the integrity of contact elements by sealing cracks and preventing interaction with the electrode metal during the removal process, ensuring reliable electrical performance in sophisticated semiconductor devices.
Implementation Method 1
A dielectric cap layer is formed above the gate electrode structure to mask the metal gate electrodes
Implementation Method 2
using established polishing processes to remove excess material
Data Source
AI summary
Superior contact elements may be formed in semiconductor devices in which sophisticated replacement gate approaches may be applied. To this end, a dielectric cap layer is provided prior to patterning the interlayer dielectric material so that any previously created cracks may be reliably sealed prior to the deposition of the contact material, while the removal of any excess portion thereof may be performed without an undue interaction with the electrode metal of the gate electrode structures. Consequently, a significantly reduced defect rate may be achieved.