Dielectric Cap Structure for Low-RC Gate Contact Formation
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Solution Overview
Problem
In semiconductor device fabrication, non-planar transistor devices face challenges in minimizing source/drain contact damage and leakage during gate contact formation, particularly due to misalignment issues, and in reducing parasitic RC delays associated with thick etch stop layers.
Innovation Solution
A nitride-based conformal layer is introduced over the source/drain structures and gate structures, providing etch selectivity and protection during gate contact formation, while a thin oxide-based cap layer is used to reduce RC delays by minimizing the dielectric constant.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thick silicon nitride etch stop layer is used, then source/drain contact damage is minimized during gate contact formation, but parasitic RC delays increase
Solution Approach 1:
The patent divides the protective layer into two separate segments: a thin oxide-based cap layer (first layer) and a nitride-based etch stop layer (second layer). The thin oxide layer minimizes RC delays while the nitride layer provides etch selectivity and protection. This segmentation allows each layer to optimize its specific function without the trade-off present in using a single thick nitride layer.
Solution Approach 2:
Different regions of the dielectric structure are assigned different material properties: the oxide-based cap layer provides low dielectric constant for reduced RC delays in critical signal paths, while the nitride-based layer provides high etch selectivity where protection is needed. This local differentiation of material quality optimizes both electrical performance and fabrication protection.
2Ease of manufacture
If traditional thick etch stop layers are used, then manufacturing robustness is improved, but device speed deteriorates due to increased RC delays
Solution Approach 1:
The protective structure is segmented into a thin oxide cap layer for speed optimization and a nitride layer for manufacturing robustness. This allows the device to achieve high speed performance while maintaining ease of manufacture through the selective etching properties of the nitride layer.
Solution Approach 2:
The patent uses a composite dielectric structure combining oxide and nitride materials, each contributing different properties: oxide provides low-k for high speed, while nitride provides etch selectivity for manufacturing robustness. This composite approach achieves both speed and ease of manufacture.
3Manufacturing precision
If misalignment protection layers are added, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The protective structure is divided into two functional segments with distinct roles: the thin oxide cap layer for precision alignment control during etching, and the nitride layer for robustness. This segmentation achieves manufacturing precision without excessive complexity.
Solution Approach 2:
The patent changes the thickness parameter of the oxide cap layer to be very thin, which minimizes its impact on device performance while maintaining its alignment control function. This parameter optimization reduces the complexity burden of having multiple protective layers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach accurately controls recess formation, minimizes source/drain contact damage, and significantly reduces parasitic delays by using a layer with a smaller dielectric constant than traditional silicon nitride etch stop layers.
Implementation Method 1
an oxide-based layer disposed over the nitride-based conformal layer... significantly reduces parasitic delays by using a layer with a smaller dielectric constant than traditional silicon nitride etch stop layers
Data Source
AI summary
A semiconductor device includes a channel structure, a first gate structure straddling the channel structure, and an epitaxial structure. The epitaxial structure is adjacent to the first gate structure and is coupled to an end of the channel structure. The semiconductor device further includes a first contact structure disposed over and in contact with the epitaxial structure and a nitride-based conformal layer extending at least over the first contact structure. The semiconductor device further includes an oxide-based layer disposed over the nitride-based conformal layer. A portion of the nitride-based conformal layer, disposed over the first contact structure, has a dip that is filled with a first portion of the oxide-based layer.