Dielectric Capping Structure for Air-Gap Interconnect Stability
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Solution Overview
Problem
As semiconductor integrated circuits (ICs) are scaled down, the increased density and reduced spacing between conductive features lead to higher parasitic capacitance, increasing power consumption and time delay, which existing low-k dielectrics struggle to effectively mitigate due to damage from fluorine-based and chlorine-based etchants during the patterning process.
Innovation Solution
The implementation of a dielectric capping layer and a self-assembled monolayer (SAM) to prevent damage from etchants, allowing for the formation of air-gaps between conductive wires, reducing capacitance and RC delay while maintaining the integrity of the conductive capping layer and wires.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If low-k dielectrics are used to reduce parasitic capacitance, then capacitance is reduced, but the dielectric material is damaged by fluorine-based and chlorine-based etchants during patterning
Solution Approach 1:
A capping layer is introduced as an intermediary protective barrier between the low-k dielectric material and the etchants. The capping layer is selectively removed after protecting the dielectric during patterning, allowing the dielectric to maintain its low-k properties without damage from fluorine-based and chlorine-based etchants
2Productivity
If spacing between conductive features is reduced to increase density, then device density is improved, but parasitic capacitance increases
Solution Approach 1:
Porous low-k dielectric materials are used to fill the reduced spacing between conductive features. The porous structure provides lower effective dielectric constant compared to solid dielectrics, enabling high device density while maintaining low parasitic capacitance through the air-filled pores that reduce the overall k-value
3Length of moving object
If conductive features are scaled down, then feature size is reduced, but capacitance between adjacent features increases
Solution Approach 1:
The dielectric constant parameter of the material between conductive features is changed by using low-k dielectric materials with k-values lower than standard silicon dioxide. This parameter change allows for reduced capacitance between scaled-down conductive features, maintaining signal integrity and reducing power consumption in miniaturized devices
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces capacitance and RC delay in the interconnect structure, enhancing the performance and reliability of the integrated chip by preventing damage to the conductive capping layer and wires during the etching process.
Implementation Method 1
a self-assembled monolayer (SAM) is selectively deposited over an upper surface of the first inter-level dielectric (ILD) structure such that the SAM is laterally offset from a top surface of each conductive capping layer
Implementation Method 2
A dielectric capping layer is selectively deposited along a top surface of each conductive capping layer
Data Source
AI summary
Some embodiments relate to an integrated chip include a conductive structure disposed within a dielectric structure. A first dielectric layer overlies the dielectric structure. A dielectric capping layer on the conductive structure. Opposing sidewalls of the dielectric capping layer are aligned with opposing sidewalls of the conductive structure. A second dielectric layer overlies the first dielectric layer and the dielectric capping layer, wherein the second dielectric layer directly contacts the opposing sidewalls of the dielectric capping layer, the opposing sidewalls of the conductive structure, and a top surface of the first dielectric layer.