Dielectric Capping Layer for Metal Arcing Protection
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Solution Overview
Problem
Multi-dimensional integrated chips face issues with edge trimming leading to metal residue, which can cause arcing during high-power processes, damaging the chips and reducing yield.
Innovation Solution
A dielectric capping structure is employed to cover areas with metal residue, specifically formed on the wafer edge or entire upper surface, using materials like silicon oxynitride, silicon nitride, or silicon dioxide, to prevent arcing and improve yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If edge trimming is performed to remove parts of the wafer, then the wafer shape is improved and manufacturing defects are reduced, but metal residue is generated which can cause arcing during high-power processes
Solution Approach 1:
A dielectric capping layer is deposited as an intermediary substance between the metal residue and the plasma environment. This capping layer acts as a mediator that prevents direct interaction between the harmful metal residue and the high-power plasma, thereby eliminating the arcing problem while preserving the benefits of edge trimming
Solution Approach 2:
The metal residue, which is initially harmful and causes arcing, is converted into a beneficial structure by being capped with dielectric material. The capped metal residue then serves as a stable, non-arcing feature that can be intentionally designed and controlled, transforming the harmful byproduct into a useful component of the wafer structure
2Reliability
If a dielectric capping structure is formed to cover metal residue, then arcing is prevented and yield is improved, but additional processing steps are required
Solution Approach 1:
The dielectric capping layer serves multiple functions simultaneously: it prevents arcing by isolating metal residue, provides a planar surface for subsequent processing, and can be integrated with existing interconnect dielectric layers. This multi-functionality reduces the need for additional specialized processing steps
3Reliability
If the entire upper surface of the wafer is capped with dielectric material, then arcing protection is maximized, but material usage and processing time increase
Solution Approach 1:
Instead of uniformly capping the entire wafer surface, the dielectric capping layer is applied selectively to areas where metal residue is present, typically the peripheral regions. This localized approach provides adequate arcing protection while minimizing dielectric material consumption and associated processing time
Data Source
AI summary
The present disclosure, in some embodiments, relates to a method of forming an integrated chip structure. The method may be performed by forming a plurality of interconnect layers within a first interconnect structure disposed over an upper surface of a first semiconductor substrate. An edge trimming process is performed to remove parts of the first interconnect structure and the first semiconductor substrate along a perimeter of the first semiconductor substrate. The edge trimming process results in the first semiconductor substrate having a recessed surface coupled to the upper surface by way of an interior sidewall disposed directly over the first semiconductor substrate. A dielectric capping structure is formed onto a sidewall of the first interconnect structure after performing the edge trimming process.