Dielectric Chiplet Interposer for Lower-Cost, Low-Stress Packaging
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving cost-effective and stress-reduced packaging techniques for semiconductor dies, particularly in advanced packaging technologies like Package-on-Package (PoP) and Chip-On-Wafer-On-Substrate (CoWoS), where silicon-based substrates are costly and stress-concentrating.
Innovation Solution
The use of a dielectric fill layer as a substrate in chiplet interposers, which omits a silicon substrate, combined with a redistribution structure formed through multiple side-by-side patterning processes, allowing for cost-effective production and reduced stress concentration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If a silicon substrate is used in chiplet interposers, then structural integrity is improved, but cost increases and stress concentration worsens
Solution Approach 1:
The patent replaces expensive silicon substrates with organic substrate materials that are cheaper and can be discarded after serving their temporary purpose as carriers during the interposer formation process, thereby reducing manufacturing cost while maintaining structural integrity during critical operations
Solution Approach 2:
The patent changes the material parameter from silicon to organic substrates, fundamentally altering the cost and stress characteristics of the interposer while maintaining the necessary structural properties through careful material selection and design
2Strength
If a silicon substrate is used in chiplet interposers, then structural integrity is improved, but stress concentration worsens
Solution Approach 1:
The patent replaces silicon substrates with organic substrate materials that have different mechanical properties, specifically lower stress concentration characteristics, while maintaining sufficient structural integrity for the interposer application
Solution Approach 2:
The patent employs organic composite substrate materials that combine multiple properties including low stress concentration, adequate mechanical strength, and compatibility with semiconductor manufacturing processes, thereby resolving the contradiction between structural integrity and stress concentration
3Adaptability or versatility
If multiple side-by-side patterning processes are used to form redistribution structure, then manufacturing flexibility is improved, but process complexity increases
Solution Approach 1:
The patent divides the redistribution structure formation into multiple separate patterning processes that can be performed side-by-side or in sequence, allowing each patterning step to be optimized independently and enabling greater manufacturing flexibility despite increased process steps
Solution Approach 2:
The patent extends the patterning process into the lateral dimension by performing multiple side-by-side patterning operations, effectively using dimensional expansion to achieve manufacturing flexibility that would be difficult to obtain through single-process modifications
Data Source
AI summary
Embodiments include packages and methods for forming packages which include interposers having a substrate made of a dielectric material. The interposers may also include a redistribution structure over the substrate which includes metallization patterns which are stitched together in a patterning process which includes multiple lateral overlapping patterning exposures.