Dielectric Chiplet Interposer for Low-Stress Large-Area Routing
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving cost-effective and stress-reduced packaging techniques for semiconductor dies, particularly in advanced packaging technologies like Package-on-Package (POP) and Chip-On-Wafer-On-Substrate (CoWoS) structures, where silicon-based substrates are costly and contribute to stress concentration.
Innovation Solution
The use of a dielectric fill layer as a substrate in chiplet interposers, which eliminates the need for a silicon substrate, reduces stress concentration, and incorporates a redistribution structure formed through multiple side-by-side patterning processes, allowing for larger metallization patterns without requiring larger exposure tools.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If silicon-based substrates are used in advanced packaging technologies, then structural support and electrical connectivity are provided, but cost increases and stress concentration occurs
Solution Approach 1:
The patent replaces expensive silicon-based substrates with cost-effective organic substrate materials that can be discarded after serving their temporary purpose in the packaging process, eliminating the need for costly silicon while maintaining structural support functionality
Solution Approach 2:
The patent changes the material parameters from silicon-based to organic-based substrates, fundamentally altering the cost and stress characteristics while maintaining the necessary structural and electrical functions through modified material composition and design
2Reliability
If silicon-based substrates are used in advanced packaging technologies, then structural support is provided, but stress concentration increases
Solution Approach 1:
The patent changes the material parameters from silicon-based to organic-based substrates, fundamentally altering the stress characteristics while maintaining the necessary structural and electrical functions through modified material composition and design
Solution Approach 2:
The patent employs composite organic substrate structures that combine multiple materials with complementary properties to distribute and reduce stress concentration while maintaining structural support, replacing homogeneous silicon substrates with engineered composite systems
3Area of stationary object
If larger exposure tools are used to form larger metallization patterns, then larger pattern sizes are achieved, but device complexity and cost increase
Solution Approach 1:
The patent divides the formation of large metallization patterns into multiple smaller, sequential patterning steps using standard-sized exposure tools, breaking down the complex task of creating large patterns into manageable segments that can be executed with existing equipment
Solution Approach 2:
The patent extends metallization patterns across multiple layers and dimensions, using vertical stacking and three-dimensional routing to achieve large effective pattern areas without requiring proportionally larger exposure tools, utilizing the third dimension to compensate for lateral size limitations
Data Source
AI summary
Embodiments include packages and methods for forming packages which include interposers having a substrate made of a dielectric material. The interposers may also include a redistribution structure over the substrate which includes metallization patterns which are stitched together in a patterning process which includes multiple lateral overlapping patterning exposures.